Search Results1-20 of  66

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  • 高木 直史 ID: 9000008219649

    Articles in CiNii:1

    • 並列計算機ソ-ティング回路の試作と評価(技術談話室) (1984)
  • 高木 直史 ID: 9000023309008

    Articles in CiNii:1

    • Bipartite Modular Multiplication (2005)
  • 高木 直史 ID: 9000023309028

    Articles in CiNii:1

    • A fast addition algorithm for elliptic curve arithmetic in GF(2n) using projective coordinates (2000)
  • 高木 直史 ID: 9000023389096

    Articles in CiNii:1

    • A Combined Circuit for Multiplication and Inversion in ${rm GF}(2^{m})$ (2008)
  • 高木 直史 ID: 9000023512349

    Articles in CiNii:1

    • Square rooting by iterative multiply-additions (1996)
  • 高木 直史 ID: 9000024692176

    Articles in CiNii:1

    • A hardware algorithm for modular multiplication/division (2005)
  • 高木 直史 ID: 9000024696948

    Articles in CiNii:1

    • A fast algorithm for multiplicative inversion in GF(2m) using normal basis (2001)
  • 高木 直史 ID: 9000024701902

    Articles in CiNii:1

    • Powering by a table look-up and a multiplication with operand modification (1998)
  • 高木 直史 ID: 9000024707808

    Articles in CiNii:1

    • A VLSI algorithm for computing the Euclidean norm of a 3D vector (2000)
  • 高木 直史 ID: 9000024714404

    Articles in CiNii:1

    • A high-speed reduced-size adder under left-to-right input arrival (1999)
  • 高木 直史 ID: 9000241952447

    Articles in CiNii:1

    • Design Method of Easily Testable Parallel Adders under Delay Constraints (2011)
  • 高木 直史 ID: 9000241952486

    Articles in CiNii:1

    • Modeling of Timing Faults and Test Generation for Single Flux Quantum Logic Circuits (2011)
  • 高木 直史 ID: 9000241957773

    Articles in CiNii:1

    • Design Method of Easily Testable Parallel Adders under Delay Constraints (2011)
  • 高木 直史 ID: 9000241957820

    Articles in CiNii:1

    • Modeling of Timing Faults and Test Generation for Single Flux Quantum Logic Circuits (2011)
  • 高木 直史 ID: 9000286971441

    Articles in CiNii:1

    • Residue Number System and Log-Depth Circuit Algorithms for Elementary Functions <Algorithms for Arithmetic Circuits 5> (1996)
  • 高木 直史 ID: 9000286971458

    Articles in CiNii:1

    • Algorithms for Elementary Function Generators <Algorithms for Arithmetic Circuits 4> (1996)
  • 高木 直史 ID: 9000286971482

    Articles in CiNii:1

    • Algorithms for Dividers <Algorithms for Arithmetic Circuits 3> (1996)
  • 高木 直史 ID: 9000286971502

    Articles in CiNii:1

    • Algorithms for Multipliers <Algorithms for Arithmetic Circuits 2> (1996)
  • 高木 直史 ID: 9000286971528

    Articles in CiNii:1

    • Algorithms for Adders <Algorithms for Arithmetic Circuits 1> (1996)
  • 高木 直史 ID: 9000321615149

    Articles in CiNii:1

    • A Comparative Evaluation of SW/HW Communication Methods on System Design Environments for Programmable SoCs (2016)
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