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  • AJIOKA YOSHIHIDE ID: 9000004334866

    LSI Product Technology Unit, Renesas Technology Corporation (2004 from CiNii)

    Articles in CiNii:12

    • A Method to Characterize Interconnect Process Parameters in 90 nm Technology LSIs (2004)
    • A Method of Clock Distribution and Skew Error Diagnosis (2000)
    • Physical Design Methodology for On-chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor (2001)
  • AJIOKA Yoshihide ID: 9000004874314

    System LSI Division, Mitsubishi Electric Corporation (2002 from CiNii)

    Articles in CiNii:2

    • A Chip Set for Programmable Real-Time MPEG2 MP@ML Video Encoder (1998)
    • Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor (2002)
  • AJIOKA Yoshihide ID: 9000005818292

    Renesas Technology Corp (2005 from CiNii)

    Articles in CiNii:1

    • A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures (2005)
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