Search Results1-20 of  77

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  • Hideharu Amano ID: 9000347539559

    Articles in CiNii:1

    • A Toolchain for Dynamic Function Off-load on CPU-FPGA Platforms (2015)
  • AMANO HIDEHARU ID: 9000001040127

    Department of Computer Science, Keio University (1999 from CiNii)

    Articles in CiNii:1

    • Design and implementation of reconfigurable sensing system for networked robots (1999)
  • AMANO HIDEHARU ID: 9000004520049

    Keio University (2003 from CiNii)

    Articles in CiNii:1

    • Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism (2003)
  • AMANO HIDEHARU ID: 9000004520055

    Department of Computer Science, Graduate School of Keio University (2003 from CiNii)

    Articles in CiNii:1

    • Performance Evaluation of Instruction Set Architecture of MBP-light : a distributed memory controller for a large scale multiprocessor (2003)
  • AMANO HIDEHARU ID: 9000017548651

    Articles in CiNii:2

    • Leakage Efficient TLB Design for Embedded Processors (2009)
    • An On/Off Link Regulation for Low-Power InfiniBand (2009)
  • AMANO HIDEHARU ID: 9000242085751

    Keio University (2013 from CiNii)

    Articles in CiNii:1

    • FOREWORD (2013)
  • AMANO Hideharu ID: 1000060175932

    Articles in CiNii:802

    • An International Symposium on Low-Power and High-Speed Chips II (Cool Chips II) (1999)
    • COOL Chips III : An International Symposium on Low-Power and High-Speed Chips (2000)
    • Parallel Logic Simulation Algorithm Based on Queries (1992)
  • AMANO Hideharu ID: 9000004802616

    Keio University (2004 from CiNii)

    Articles in CiNii:6

    • Message Transfer Algorithms on the Recursive Diagonal Torus (1996)
    • The RDT Router Chip: A Versatile Router for Supporting a Distributed Shared Memory (1997)
    • Wavelength Division Multiple Access Ring - Virtual Toplogy on a Simple Ring Network - (1998)
  • AMANO Hideharu ID: 9000004803510

    Department of Computer Science, Keio University (1996 from CiNii)

    Articles in CiNii:1

    • The MDX (Multi-Dimensional X'bar): A Class of Networks for Large Scale Multiprocessors (1996)
  • AMANO Hideharu ID: 9000004803561

    Department of Computer Science, Keio University (1996 from CiNii)

    Articles in CiNii:1

    • Fault Tolerance of the TBSF (Tandem Banyan Switching Fabrics) and PBSF (Piled Banyan Switching Fabrics) (1996)
  • AMANO Hideharu ID: 9000004804414

    the Department of Computer Science, Keio University (1997 from CiNii)

    Articles in CiNii:1

    • MINC: Multistage Interconnection Network with Cache Control Mechanism (1997)
  • AMANO Hideharu ID: 9000004832984

    Department of Computer Science, Keio University (2003 from CiNii)

    Articles in CiNii:1

    • Performance Evaluation of Instruction Set Architecture of MBP-Light in JUMP-1 (2003)
  • AMANO Hideharu ID: 9000004833010

    Dept. of Information and Computer Science, Keio University (2003 from CiNii)

    Articles in CiNii:1

    • Pot: A General Purpose Monitor for Parallel Computers (2003)
  • AMANO Hideharu ID: 9000004833497

    Department of Information and Computer Science, Keio University (2003 from CiNii)

    Articles in CiNii:1

    • Design and Implementation of RHiNET-2/NI0: A Reconfigurable Network Interface for Cluster Computing (2003)
  • AMANO Hideharu ID: 9000004833528

    Department of Information and Computer Science, Keio University (2003 from CiNii)

    Articles in CiNii:1

    • Implementation of Data Driven Applications on a Multi-Context Reconfigurable Device (2003)
  • AMANO Hideharu ID: 9000004835947

    the Department of Information and Computer Science, Keio University (2005 from CiNii)

    Articles in CiNii:1

    • MMLRU Selection Function : A Simple and Efficient Output Selection Function in Adaptive Routing (2005)
  • AMANO Hideharu ID: 9000004880604

    Department of Computer Science, Keio University (2003 from CiNii)

    Articles in CiNii:1

    • A Dynamically Adaptive Hardware on Dynamically Reconfigurable Processor (2003)
  • AMANO Hideharu ID: 9000006192253

    Graduate School of Science and Technology, Keio University (2008 from CiNii)

    Articles in CiNii:3

    • Performance Evaluation of Hardware Multi-process Execution on the Dynamically Reconfigurable Processor (2006)
    • Reducing Power of TLB with Power-Gating Technique on Microprocessor (2008)
    • Cache Controller Design With Run-time Power Gating (2008)
  • AMANO Hideharu ID: 9000006192266

    Faculty of Science and Technology, Keio University (2011 from CiNii)

    Articles in CiNii:12

    • A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs (2009)
    • A Leakage Efficient Data TLB Design for Embedded Processors (2011)
    • A Leakage Efficient Instruction TLB Design for Embedded Processors (2011)
  • AMANO Hideharu ID: 9000006660502

    Graduate School of Science and Technology, Keio University (2008 from CiNii)

    Articles in CiNii:1

    • A Method for Saving and Restoring Context Data of Hardware Tasks on the Dynamically Reconfigurable Processor (2008)
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