Search Results1-20 of  111

  • Asada Kunihiro ID: 9000404110991

    VLSI Design and Education Center, the University of Tokyo|Dept. of Electrical Engineering and Information Systems, the University of Tokyo (2019 from CiNii)

    Articles in CiNii:1

    • Spatial Resolution Improvement for Point Light Source Detection in Scintillator Cube using SPAD Array with Multi Pinholes (2019)
  • ASADA Kunihiro ID: 9000000522128

    Faculty of Engineering, The University of Tokyo (1992 from CiNii)

    Articles in CiNii:1

    • -1/5 Power Law in PN-Junction Failure Mechanism Caused by Electrical-Over-Stress (1992)
  • ASADA Kunihiro ID: 9000001663859

    the VLSI Design and Education Center (VDEC), The University of Tokyo (2012 from CiNii)

    Articles in CiNii:29

    • Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs(<Special Section>Papers Selected from AP-ASIC 2004) (2005)
    • Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization(VLSI Design Technology and CAD) (2005)
    • Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability (2009)
  • ASADA Kunihiro ID: 9000001728109

    The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC) (2006 from CiNii)

    Articles in CiNii:2

    • Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme in SOI Technology (2006)
    • Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme in SOI Technology (2006)
  • ASADA Kunihiro ID: 9000004791020

    Faculty of Engineering, and VLSI Design and Education Center (VDEC), the University of Tokyo (2004 from CiNii)

    Articles in CiNii:6

    • Wide Dynamic Range Photo Detector for Smart Position Sensor Using Log-Response and Correlation Circuit (2001)
    • A Synchronous Completion Prediction Adder (SCPA) (1997)
    • A Row-Parallel Position Detector for High-Speed 3-D Camera Based on Light-Section Method (2003)
  • ASADA Kunihiro ID: 9000004797521

    VLSI Design and Education Center, the University of Tokyo (2001 from CiNii)

    Articles in CiNii:1

    • A System Level Optimization Technique for Application Specific Low Power Memories (2001)
  • ASADA Kunihiro ID: 9000004799001

    The author is with the VLSI Design and Education Center, The University of Tokyo (2001 from CiNii)

    Articles in CiNii:1

    • Functional Decomposition with Application to LUT-Based FPGA Synthesis (2001)
  • ASADA Kunihiro ID: 9000004810573

    Faculty of Engineering, The University of Tokyo (1995 from CiNii)

    Articles in CiNii:1

    • Data Bypassing Register File for Low Power Microprocessor (1995)
  • ASADA Kunihiro ID: 9000004811567

    Faculty of Engineering, The University of Tokyo (1995 from CiNii)

    Articles in CiNii:1

    • A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability (1995)
  • ASADA Kunihiro ID: 9000004812880

    Faculty of Engineering, The University of Tokyo (1996 from CiNii)

    Articles in CiNii:1

    • Modeling of Leak Current Characteristics in High Frequency Operation of CMOS Circuits Fabricated on SOI Substrate (1996)
  • ASADA Kunihiro ID: 9000004813203

    Faculty of Engineering, The University of Tokyo (1996 from CiNii)

    Articles in CiNii:1

    • Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors (1996)
  • ASADA Kunihiro ID: 9000004815071

    Department of Electronic Engineering, Faculty of Engineering, University of Tokyo (1997 from CiNii)

    Articles in CiNii:1

    • Design of High-Speed High-Density Parallel Adders and Multipliers Using Regenerative Pass-Transistor Logic (1997)
  • ASADA Kunihiro ID: 9000004815594

    VLSI Design and Education Center, The University of Tokyo (1997 from CiNii)

    Articles in CiNii:1

    • Device Parameter Estimation of SOI MOSFET Using One-Dimensional Numerical Simulation Considering Quantum Mechanical Efects (1997)
  • ASADA Kunihiro ID: 9000004815767

    School of Engineering, the University of Tokyo (VLSI Design and Education Center, University of Tokyo) (1997 from CiNii)

    Articles in CiNii:1

    • An Image Scanning Method with Selective Activation of Tree Structure (1997)
  • ASADA Kunihiro ID: 9000004815836

    Department of Electronic Engineering, the University of Tokyo (1997 from CiNii)

    Articles in CiNii:1

    • Power Optimization for Data Compressors Based on a Window Detector in a 54×54 Bit Multiplier (1997)
  • ASADA Kunihiro ID: 9000004816464

    the Department of Electronic Engineering, University of Tokyo (1998 from CiNii)

    Articles in CiNii:1

    • Design of Low Power Digital VLSI Circuits Based on a Novel Pass-Transistor Logic (1998)
  • ASADA Kunihiro ID: 9000004820800

    VLSI Design and Education Center, The University of Tokyo (2000 from CiNii)

    Articles in CiNii:1

    • Approaches for Reducing Power Consumption in VLSI Bus Circuits (2000)
  • ASADA Kunihiro ID: 9000004826225

    VLSI Design and Education Center (VDEC), The University of Tokyo (2002 from CiNii)

    Articles in CiNii:1

    • Design of a Conditional Sign Decision Booth Encoder for a High Performance 32×32-Bit Digital Multiplier (2002)
  • ASADA Kunihiro ID: 9000004873870

    the Department of Electronic Engineering, Faculty of Engineering, the University of Tokyo (1996 from CiNii)

    Articles in CiNii:1

    • Regenerative Pass-Transistor Logic: A Circuit Technique for High Speed Digital Design (1996)
  • ASADA Kunihiro ID: 9000004874855

    Faculty of Engineering, The Univ. of Tokyo (VDEC, Univ. of Tokyo) (1999 from CiNii)

    Articles in CiNii:1

    • Test Structure for Characterizing Capacitance Matrix of Multi-Layer Interconnects in VLSI (1999)
Page Top