Search Results1-20 of  33

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  • CHO Byung Jin ID: 9000002166656

    Silicon Nano Device Laboratory, Dept. of Electrical & Computer Engineering, NUS (2004 from CiNii)

    Articles in CiNii:1

    • Behavior of Effective Work Function in Metal/High-K Gate Stack under High Temperature Process (2004)
  • CHO Byung Jin ID: 9000002168126

    Silicon Nano Device Lab, Dept. of Electrical & Computer Engineering, National University of Singapore (2004 from CiNii)

    Articles in CiNii:1

    • Top-Surface Aluminized and Nitrided Hafnium Oxide Using Synthesis of Thin AlN and HfO_2 Stacked Layer (2004)
  • CHO Byung Jin ID: 9000002175001

    Silicon Nano Device Lab, Dept of ECE, National University of Singapore (2007 from CiNii)

    Articles in CiNii:1

    • Integration of Dual Channels MOSFET on Defect-Free, Tensile-Strained Germanium on Silicon (2007)
  • CHO Byung Jin ID: 9000005840647

    Center for Integrated Circuit Failure Analysis and Reliability, Department of Electrical and Computer Engineering, National University of Singapore (2002 from CiNii)

    Articles in CiNii:4

    • Gate Oxide Reliability Concern Associated with X-Ray Lithography (2000)
    • Intergrity of Gate Oxides Irradiated Under Electron-Beam Lithography Conditions (1999)
    • Hot-Carrier Lifetime Dependence on Channel Width and Silicon Recess Depth in N-Channel Metal-Oxide-Semiconductor Field-Effect-Transistors with the Recessed Local Oxidation of Silicon Isolation Structure (2002)
  • CHO Byung Jin ID: 9000006460837

    Silicon Nano Device Lab (SNDL). Department of Electrical and Computer Engineering. National University of Singapore (2002 from CiNii)

    Articles in CiNii:1

    • Investigation of Quasi-Breakdown Mechanism through Post-Quasi-Breakdown Thermal Annealing (2002)
  • CHO Byung Jin ID: 9000006838950

    Articles in CiNii:2

    • High-K Dielectrics for Charge Trap - type Flash Memory Application (2008)
    • High-K Dielectrics for Charge Trap-type Flash Memory Application (2008)
  • CHO Byung Jin ID: 9000015605571

    Silicon Nano Device Lab (SNDL), Department of Electrical and Computer Engineering, National University of Singapore (2003 from CiNii)

    Articles in CiNii:1

    • Dependence of Chemical Composition Ratio on Electrical Properties of HfO_2-Al_2O_3 Gate Dielectric (2003)
  • CHO Byung Jin ID: 9000017504548

    Department of Electrical Engineering, KAIST (2010 from CiNii)

    Articles in CiNii:1

    • Synthesis of wafer scale graphene layer for future electronic devices (2010)
  • CHO Byung Jin ID: 9000017504919

    Department of Electrical Engineering, KAIST (2010 from CiNii)

    Articles in CiNii:1

    • Synthesis of wafer scale graphene layer for future electronic devices (2010)
  • CHO Byung Jin ID: 9000017674134

    Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (2010 from CiNii)

    Articles in CiNii:1

    • Cubic-Structured HfLaO for the Blocking Layer of a Charge-Trap Type Flash Memory Device (2010)
  • CHO Byung Jin ID: 9000107334553

    Department of Electrical and Computer Engineering, National University of Singapore (2001 from CiNii)

    Articles in CiNii:1

    • Reliability of Thin Gate Oxides Irradiated under X-Ray Lithography Conditions (2001)
  • CHO Byung Jin ID: 9000107365471

    Department of Electrical Engineering, KAIST (2012 from CiNii)

    Articles in CiNii:1

    • Improvement of Charge Retention in Flash Memory Devices by Very Light Doping of Lanthanum into an Aluminum-Oxide Blocking Layer (2012)
  • CHO Byung-Jin ID: 9000005718039

    Memory R&D Division, HYUNDAI Electronics Ind. Co. Ltd. (1997 from CiNii)

    Articles in CiNii:2

    • Double Spacer LOCOS Process with Shallow Recess of Silicon for 0.20μm Isolation (1996)
    • Evaluation of Double Spacer Local Oxidation of Silicon(LOCOS) Isolation Process for Sub-Quarter Micron Design Rule (1997)
  • CHO Byung-Jin ID: 9000005908361

    Deptartment of Electrical and Computer Engineering. National University of Singapore (2002 from CiNii)

    Articles in CiNii:3

    • A Strong Temperature-Dependent Hole Direct Tunneling Current in p^+-Gate/pMOSFET with Ultra-Thin Gate Oxide (2000)
    • Negative Bias Temperature Instability on Plasma-Nitrided Silicon Dioxide Film (2002)
    • Reduction of Radiation-Induced Leakage Currents in Thin Oxides by Application of a Low Post-Irradiation Gate Bias (2000)
  • Cho Byung Jin ID: 9000258151612

    Department of Electrical Engineering, National University of Singapore, 10 Kent Ridge Crescent, Singapore 119260 (2000 from CiNii)

    Articles in CiNii:1

    • Investigation of Reliability Degradation of Ultra-Thin Gate Oxides Irradiated under Electron-Beam Lithography Conditions. (2000)
  • Cho Byung Jin ID: 9000258161448

    Silicon Nano Device Lab (SNDL), Department of Electrical and Computer Engineering, National University of Singapore, 10 Kent Ridge Crescent, Singapore 119260 (2002 from CiNii)

    Articles in CiNii:1

    • Investigation of Quasi-Breakdown Mechanism through Post-Quasi-Breakdown Thermal Annealing. (2002)
  • Cho Byung Jin ID: 9000283187726

    Silicon Nano Device Lab (SNDL), Department of Electrical and Computer Engineering, National University of Singapore (2003 from CiNii)

    Articles in CiNii:1

    • Dependence of Chemical Composition Ratio on Electrical Properties of HfO2-Al2O3 Gate Dielectric. (2003)
  • Cho Byung Jin ID: 9000401568703

    Articles in CiNii:1

    • Cubic-Structured HfLaO for the Blocking Layer of a Charge-Trap Type Flash Memory Device (2010)
  • Cho Byung Jin ID: 9000401573496

    Articles in CiNii:1

    • Improvement of Charge Retention in Flash Memory Devices by Very Light Doping of Lanthanum into an Aluminum-Oxide Blocking Layer (2012)
  • Cho Byung Jin ID: 9000401688410

    Articles in CiNii:1

    • Investigation of Reliability Degradation of Ultra-Thin Gate Oxides Irradiated under Electron-Beam Lithography Conditions (2000)
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