Search Results1-10 of  10

  • Choi Byung Yong ID: 9000009195898

    Articles in CiNii:1

    • Side-gate Length Optimization for 50nm Induced Source/ Drain MOSFETs (2001 Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices(AWAD 2001)) (2001)
  • Choi Byung Yong ID: 9000024936672

    Articles in CiNii:1

    • Highly Manufacturable and Reliable 80-nm Gate Twin Silicon-Oxide-Nitride-Oxide-Silicon Memory Transistor (2005)
  • CHOI Byung Yong ID: 9000004746204

    Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University (2004 from CiNii)

    Articles in CiNii:11

    • 70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As^+_2 Low Energy Implantations (2001)
    • Side-Gate Design for 50nm Electrically Induced Source/Drain MOSFETs (2001)
    • 70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As_2^+ Å Low Energy Ion Implantations (2000)
  • CHOI Byung Yong ID: 9000107389434

    Inter-University Semiconductor Research Center, Seoul National University (2004 from CiNii)

    Articles in CiNii:1

    • Stable Extraction of Threshold Voltage Using Transconductance Change Method for CMOS Modeling, Simulation and Characterization (2004)
  • Choi Byung Yong ID: 9000258161076

    Inter-University Semiconductor Research Center, Seoul National University, Kwanak-ku, Seoul 151-742, Korea|School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-ku, Seoul 151-742, Korea (2002 from CiNii)

    Articles in CiNii:1

    • Side-Gate Design Optimization of 50 nm MOSFETs with Electrically Induced Source/Drain. (2002)
  • Choi Byung Yong ID: 9000258179741

    School of Electrical Engineering and Computer Science, Seoul National University (2005 from CiNii)

    Articles in CiNii:1

    • Highly Manufacturable and Reliable 80-nm Gate Twin Silicon-Oxide-Nitride-Oxide-Silicon Memory Transistor (2005)
  • Choi Byung Yong ID: 9000401697820

    Articles in CiNii:1

    • 70 nm NMOSFET Fabrication with 12 nm n+-p Junctions Using As2+Low Energy Implantations (2001)
  • Choi Byung Yong ID: 9000401705962

    Articles in CiNii:1

    • Side-Gate Design Optimization of 50 nm MOSFETs with Electrically Induced Source/Drain (2002)
  • Choi Byung Yong ID: 9000401743234

    Articles in CiNii:1

    • Highly Manufacturable and Reliable 80-nm Gate Twin Silicon-Oxide-Nitride-Oxide-Silicon Memory Transistor (2005)
  • Choi Byung Yong ID: 9000401778444

    Articles in CiNii:1

    • Improving Read Disturb Characteristics by Self-Boosting Read Scheme for Multilevel NAND Flash Memories (2009)
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