Search Results1-20 of  31

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  • Masato Edahiro ID: 9000346958468

    Articles in CiNii:1

    • System-level Design Method for Control Systems with Hardware-implemented Interrupt Handler （2015）
  • Masato Edahiro ID: 9000347539540

    Articles in CiNii:1

    • Editor's Message to Special Issue on Embedded Systems Engineering （2015）
  • Masato Edahiro ID: 9000347540147

    Articles in CiNii:1

    • Editor's Message to Special Issue of Embedded Systems Engineering （2015）
  • Masato Edahiro ID: 9000347540151

    Articles in CiNii:1

    • System-level Design Method for Control Systems with Hardware-implemented Interrupt Handler （2015）
  • EDAHIRO Masato ID: 9000004472905

    Articles in CiNii:5

    • Bucketing Techniques and an Algorithm for LSI Layout Pattern Design （1986）
    • A placement Algorithm for Sea-of-gates Layouts （1991）
    • An Interactive DRC Algorithm and a Design-Rule Representation Method for VLSI Layout Verification （1989）
  • EDAHIRO Masato ID: 9000004474357

    C&C Media Research Laboratories, NEC Corporation （2000 from CiNii）

    Articles in CiNii:4

    • PROCEED-LED : An LSI Layout Editor （1988）
    • Representation and Analysis of Fault-Tolerant Systems using Domain-Partition Model （1995）
    • Representation and Analysis of Fault-Tolerant Systems using Domain-Partition Model （1995）
  • EDAHIRO Masato ID: 9000004793492

    C&C Media Research Laboratories, NEC Corporation （1999 from CiNii）

    Articles in CiNii:1

    • A VLSI Scan-Chain Optimization Algorithm for Multiple Scan-Paths （1999）
  • EDAHIRO Masato ID: 9000004798240

    Articles in CiNii:1

    • Special Section on Discrete Mathematics and Its Applications （2001）
  • EDAHIRO Masato ID: 9000004824847

    The authors are with Silicon Systems Research Laboratories, System Devices and Fundamental Research, NEC Corporation （2001 from CiNii）

    Articles in CiNii:1

    • An Area-Effective Datapath Architecture for Embedded Microprocessors and Scalable Systems （2001）
  • EDAHIRO Masato ID: 9000004954556

    System Devices Res. Labs, NEC Corporation （2007 from CiNii）

    Articles in CiNii:6

    • Clock Tree Synthesis for Shrinking a Chip Design （2000）
    • Clock Tree Synthesis for Shrinking a Chip Design （2000）
    • Map Sort : A Scalable Sorting Algorithm for Multi-Core Processors （2007）
  • EDAHIRO Masato ID: 9000016852299

    Graduate School of Information Science, Nagoya University （2012 from CiNii）

    Articles in CiNii:3

    • New Side Channel Attack Countermeasure Based on Minimal Hamming Weight Distribution (Mathematical Foundation of Algorithms and Computer Science) （2010）
    • Dynamic Programming Algorithm for Optimal Double-Base Chains : Extended Abstract (Mathematical Foundations and Applications of Computer Science and Algorithms) （2011）
    • Optimal Average Joint Hamming Weight for Asymmetric Representation （2012）
  • EDAHIRO Masato ID: 9000018481724

    Articles in CiNii:8

    • Designing Evaluation Functions of Multi Core Task Mapping for Hard Real-Time Systems （2011）
    • Designing Evaluation Functions of Multi Core Task Mapping for Hard Real-Time Systems （2011）
    • Parallel C code generation from Simulink models （2011）
  • EDAHIRO Masato ID: 9000237756853

    Graduate School of Information Science Nagoya University （2012 from CiNii）

    Articles in CiNii:1

    • Implementation and evaluation of the AES/ADPCM on STP and FPGA with Behavioral Synthesis （2012）
  • EDAHIRO Masato ID: 9000242790647

    名古屋大学情報科学研究科 （2015 from CiNii）

    Articles in CiNii:10

    • Cyber-Physical Systems and LSI Design Technologies （2013）
    • 階層構造を持つメニーコアアーキテクチャへのタスクマッピング （2014）
    • モデル予測制御における非線形漸化式実行の並列化 （2015）
  • EDAHIRO Masato ID: 9000282785364

    Nagoya University （2013 from CiNii）

    Articles in CiNii:1

    • System-level design method considering the interrupt processing （2013）
  • EDAHIRO Masato ID: 9000285078911

    Nagoya University （2013 from CiNii）

    Articles in CiNii:1

    • System-level design method considering the interrupt processing （2013）
  • EDAHIRO Masato ID: 9000318582707

    Nagoya University （2016 from CiNii）

    Articles in CiNii:1

    • Parallel Design of Feedback Control Systems Utilizing Dead Time for Embedded Multicore Processors （2016）
  • EDAHIRO Masato ID: 9000405894557

    Graduate School of Information Science, Nagoya University （2020 from CiNii）

    Articles in CiNii:1

    • An Open Multi-Sensor Fusion Toolbox for Autonomous Vehicles （2020）
  • Edahiro Masato ID: 9000004152227

    Articles in CiNii:44

    • Performance-Driven CAD : Delay-Estimation Models （1995）
    • A Chip Multiprocessor Platform for Mobile Terminals Toward Coordination with Home Appliances （2005）
    • A Chip Multiprocessor Platform for Mobile Terminals Toward Coordination with Home Appliances （2005）
  • Edahiro Masato ID: 9000004845007

    C&C Research Laboratories, NEC Corporation （1994 from CiNii）

    Articles in CiNii:1

    • Practical Efficiencies of Planar Point Location Algorithms (Special Section on Discrete Mathematics and Its Applications) （1994）
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