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  • FURUTANI Kiyohiro ID: 9000004781189

    Articles in CiNii:5

    • スキュー及びジッターを低減可能な,DDR-SDRAMに適したDLL回路構成に関する提案 (2000)
    • Skew and Jitter Suppressed DLL Architecture for Over 400 Mbps DDR SDRAMs (2000)
    • Skew and Jitter Suppressed DLL Architecture for Over 400Mbps DDR SDRAMs (2000)
  • FURUTANI Kiyohiro ID: 9000004811963

    ULSI Laboratory, Mitsubishi Electric Corporation (1997 from CiNii)

    Articles in CiNii:5

    • A Mixed-Mode Voltage Down Converter with Impedance Adjustment Circuitry for Low-Voltage High-Frequency Memories (1996)
    • Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs (1995)
    • A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs (1997)
  • FURUTANI Kiyohiro ID: 9000004842619

    Memory Development Dept., Renesas Technology Corporation (2005 from CiNii)

    Articles in CiNii:1

    • Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories (2005)
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