Search Results1-20 of  36

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  • HARIYAMA Masanori ID: 1000010292260

    Graduate School of Information Sciences, Tohoku University (2014 from CiNii)

    Articles in CiNii:156

    • Design of a Motion Stereo VLSI Processor Based on a Transfer Bottleneck-Free Sensor/Memory Architecture (2000)
    • Implementation of an Ultra-High-Speed Path Planning VLSI Processor Using a ROM-Type Content-Addressable Memory (2001)
    • リアルワールド応用知能集積システムの展望 (2001)
  • HARIYAMA Masanori ID: 9000002298091

    Graduate School of Information Sciences, Tohoku University (2012 from CiNii)

    Articles in CiNii:19

    • Architecture of a high-performance stereo vision VLSI processor (2000)
    • Memory Allocation for Multi-Resolution Image Processing (2008)
    • Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment (2008)
  • HARIYAMA Masanori ID: 9000004820045

    Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University (1999 from CiNii)

    Articles in CiNii:1

    • Collision Detection VLSI Processor for Intelligent Vehicles Using a Hierarchically-Content-Addressable Memory (1999)
  • HARIYAMA Masanori ID: 9000004983683

    Graduate School of Information Sciences, Tohoku University (2003 from CiNii)

    Articles in CiNii:1

    • C-12-4 Low Power Field Programmable VLSI Processor Using Multiple Supply Voltages (2003)
  • HARIYAMA Masanori ID: 9000006046017

    北海道東海大学海洋開発工学科 (2005 from CiNii)

    Articles in CiNii:1

    • Weight of Stable Connected-cncrete Blocks by Wave Model Test (2005)
  • HARIYAMA Masanori ID: 9000016493965

    Graduate School of Information Sciences, Tohoku University (2006 from CiNii)

    Articles in CiNii:1

    • Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification (2006)
  • HARIYAMA Masanori ID: 9000016494069

    Graduate Shcool of Information Sciences, Tohoku University (2006 from CiNii)

    Articles in CiNii:1

    • A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates (2006)
  • HARIYAMA Masanori ID: 9000017683333

    Graduate School of Information Sciences, Tohoku University (2008 from CiNii)

    Articles in CiNii:1

    • Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling (2008)
  • HARIYAMA Masanori ID: 9000021447191

    Articles in CiNii:1

    • Pixel-Serial and Window-Parallel VLSI Processor for Stereo Matching Using a Variable Window Size (2001)
  • HARIYAMA Masanori ID: 9000021557910

    Articles in CiNii:1

    • Collision Detection VLSI Processor for Highly-Safe Intelligent Vehicles Using a Multiport Content-Addressable Memory. (1999)
  • HARIYAMA Masanori ID: 9000021582648

    Articles in CiNii:1

    • Design Methodology for Human-Oriented Intelligent Integrated Systems (2001)
  • HARIYAMA Masanori ID: 9000021797312

    Graduate School of Information Sciences, Tohoku University (2012 from CiNii)

    Articles in CiNii:1

    • Platform and Mapping Methodology for Heterogeneous Multicore Processors (2012)
  • HARIYAMA Masanori ID: 9000107367175

    Articles in CiNii:1

    • Acceleration of Block Matching by using Multiple Alignments on Heterogeneous Multi-Core Processor (2011)
  • HARIYAMA Masanori ID: 9000107382019

    Articles in CiNii:1

    • Design of a Multi-Context Field Programmable VLSI Using Ferroelectric-Based Functional Pass-Gates (2008)
  • HARIYAMA Masanori ID: 9000107382095

    Articles in CiNii:1

    • Architecture of a Stereo Matching VLSI Based on Recursive Computation (2008)
  • HARIYAMA Masanori ID: 9000240076581

    Graduate School of Information Sciences, Tohoku University (2013 from CiNii)

    Articles in CiNii:1

    • Architecture of an Asynchronous FPGA for Handshake-Component-Based Design (2013)
  • HARIYAMA Masanori ID: 9000240538643

    the Graduate School of Information Sciences, Tohoku University (2012 from CiNii)

    Articles in CiNii:1

    • Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates (2012)
  • HARIYAMA Masanori ID: 9000242085204

    Graduate School of Information Sciences, Tohoku University (2013 from CiNii)

    Articles in CiNii:1

    • Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators (2013)
  • HARIYAMA Masanori ID: 9000245825396

    Articles in CiNii:1

    • Platform and Mapping Methodology for Heterogeneous Multicore Processors (2012)
  • HARIYAMA Masanori ID: 9000258734161

    the Graduate School of Information Sciences, Tohoku University (2012 from CiNii)

    Articles in CiNii:1

    • Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation (2012)
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