Search Results1-13 of  13

  • HOSOKAWA Toshinori ID: 9000004234510

    Articles in CiNii:88

    • An Evaluation of the Effects for Hardware Trojan Designs in AES Encryption Circuits (2012)
    • A decision method of target detected pseudo primary outputs on Low-capture-swithing-activity test generation (2010)
    • A Binding Method for Testability to Generate Easily Testable Functional Time Expansion Models (2016)
  • HOSOKAWA Toshinori ID: 9000004797498

    Corporate Development Division, Semiconductor Company, Matsushita Electric Industrial Co., Ltd.:Design Technology Development Department, Semiconductor Technology Academic Research Center (2001 from CiNii)

    Articles in CiNii:1

    • Novel DFT Strategies Using Full/Partial Scan Designs and Test Point Insertion to Reduce Test Application Time (2001)
  • HOSOKAWA Toshinori ID: 9000004869483

    Corporate Semiconductor Development Division, Matsushita Electric Industrial Co., Ltd. (1998 from CiNii)

    Articles in CiNii:1

    • Partial Scan Design Methods Based on n-Fold Line-Up Structures and the State Justification of Pure Load/Hold Flip-Flops (1998)
  • HOSOKAWA Toshinori ID: 9000017682787

    College of Industrial Technology, Nihon University (2010 from CiNii)

    Articles in CiNii:1

    • A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint (2010)
  • HOSOKAWA Toshinori ID: 9000107314870

    College of Industrial Technology, Nihon University (2011 from CiNii)

    Articles in CiNii:1

    • A study on path selection results of an adaptive field test with process variation and aging degradation for VLSI (2011)
  • HOSOKAWA Toshinori ID: 9000107315158

    College of Industrial Technology, Nihon University (2011 from CiNii)

    Articles in CiNii:1

    • A scan chain construction method to reduce test data volume on BAST (2011)
  • HOSOKAWA Toshinori ID: 9000107318345

    College of Industrial Technology, Nihon University (2012 from CiNii)

    Articles in CiNii:1

    • A method to reduce the number of testpatterns for transition faults using control point insertions (2012)
  • HOSOKAWA Toshinori ID: 9000107319174

    College of Industrial Technology, Nihon University (2011 from CiNii)

    Articles in CiNii:1

    • A study on path selection results of an adaptive field test with process variation and aging degradation for VLSI (2011)
  • HOSOKAWA Toshinori ID: 9000107320426

    College of Industrial Technology, Nihon University (2011 from CiNii)

    Articles in CiNii:1

    • A scan chain construction method to reduce test data volume on BAST (2011)
  • HOSOKAWA Toshinori ID: 9000240076708

    College of Industrial Technology, Nihon University (2013 from CiNii)

    Articles in CiNii:1

    • A Test Compaction Oriented Don't Care Identification Method Based on X-bit Distribution (2013)
  • HOSOKAWA Toshinori ID: 9000365542343

    College of Industrial Technology, Nihon University (2017 from CiNii)

    Articles in CiNii:1

    • A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation (2017)
  • HOSOKAWA Toshinori ID: 9000375905577

    College of Industrial Technology, Nihon University (2017 from CiNii)

    Articles in CiNii:1

    • A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT (2017)
  • Toshinori Hosokawa ID: 9000004333882

    STARC (2004 from CiNii)

    Articles in CiNii:5

    • A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint (2003)
    • A Test State Reduction Method for FSMs with Non-Scan DFT Using Don't Care Inputs Identification Technique (2003)
    • A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint(Test)(<Special Issue>Dependable Computing) (2003)
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