Search Results1-20 of  101

  • Ishihara Tohru ID: 9000379569682

    Articles in CiNii:1

    • Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories （2008）
  • Ishihara Tohru ID: 9000403554956

    Articles in CiNii:1

    • Row/Column Redundancy to Reduce SRAM Leakage in Presence of Random Within-Die Delay Variation （2008）
  • Ishihara Tohru ID: 9000403554993

    Articles in CiNii:1

    • The Energy Reduction of Embedded Processors Using Cache Way Assignment and Code Placement （2008）
  • Ishihara Tohru ID: 9000403554999

    Articles in CiNii:1

    • An Optimization Technique of Code Allocation and Memory Configuration for Low Power Embedded Memory Systems （2008）
  • Ishihara Tohru ID: 9000403555362

    Articles in CiNii:1

    • A Single Cycle Accessible Two-Level Cache Architecture for Reducing the Energy Consumption of Embedded Systems （2008）
  • Ishihara Tohru ID: 9000403557397

    Articles in CiNii:1

    • Combining multiple gated flip-flops for saving the register power consumption （2009）
  • Ishihara Tohru ID: 9000403558897

    Articles in CiNii:1

    • Optimal Stack Frame Placement and Transfer for Energy Reduction Targeting Embedded Processors with Scratch-Pad Memories （2010）
  • Ishihara Tohru ID: 9000403558966

    Articles in CiNii:1

    • An Implementation of Energy Efficient Multi-performance Processor for Real-Time Applications （2010）
  • Ishihara Tohru ID: 9000403558976

    Articles in CiNii:1

    • Compiler Assisted Energy Reduction Techniques for Embedded Multimedia Processors （2010）
  • Tohru Ishihara ID: 9000018481705

    Articles in CiNii:2

    • An Energy Optimization Framework for Embedded Applications （2011）
    • An Energy Optimization Framework for Embedded Applications （2011）
  • ISHIHARA TOHRU ID: 9000241456192

    Articles in CiNii:1

    • An Optimization Technique for Low-Energy Embedded Memory Systems (IPSJ Transactions on System LSI Design Methodology Vol.2) （2009）
  • ISHIHARA TOHRU ID: 9000241456270

    Articles in CiNii:1

    • Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion (IPSJ Transactions on System LSI Design Methodology Vol.2) （2009）
  • Tohru Ishihara ID: 9000404086279

    Articles in CiNii:1

    • A Process-Scheduler-Based Approach to Minimum Energy Point Tracking （2019）
  • Tohru Ishihara ID: 9000404307960

    Articles in CiNii:1

    • A Software Implementation of Minimum Energy Point Tracking Algorithm for Microprocessors （2018）
  • ISHIHARA TOHRU ID: 9000001483706

    Department of Surgery Shirahigebashi Hospital （1997 from CiNii）

    Articles in CiNii:1

    • Squamous Cell Carcinoma of the Pancreas Accompanied by Mucinous Cystadenocarcinoma : A Case Report of an Unusual Association （1997）
  • ISHIHARA TOHRU ID: 9000272644631

    Department of Communications and Computer Engineering Graduate School of Informatics, Kyoto University （2014 from CiNii）

    Articles in CiNii:1

    • Evaluation of Charge Scheduling on a Multi-Banked Supercapacitor Architecture for Energy Harvesting Embedded Systems （2014）
  • ISHIHARA TOHRU ID: 9000272645996

    Department of Communications and Computer Engineering Graduate School of Informatics, Kyoto University （2014 from CiNii）

    Articles in CiNii:1

    • Evaluation of Charge Scheduling on a Multi-Banked Supercapacitor Architecture for Energy Harvesting Embedded Systems （2014）
  • ISHIHARA Tohru ID: 1000030323471

    Articles in CiNii:108

    • A Reliability Evaluation Technique for Soft-Error Susceptible Computer Systems （2005）
    • A Code Placement Technique for Improving the Performance Yield of Processors with Defective Caches （2005）
    • A Reliability Evaluation Technique for Soft-Error Susceptible Computer Systems （2006）
  • ISHIHARA Tohru ID: 9000000413257

    Department of Bioscience and Biotechnology, Shinshu University （1997 from CiNii）

    Articles in CiNii:2

    • Purification and Characterization of Polyamine Aminotransferase of Arthrobacter sp. TMP-1^1 （1997）
    • Action of Polyamine Aminotransferase on Norspermidine （1997）
  • ISHIHARA Tohru ID: 9000004793373

    Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University （1999 from CiNii）

    Articles in CiNii:1

    • A Memory Power Optimization Technique for Application Specific Embedded Systems （1999）
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