Search Results1-20 of  94

  • 1 / 5
  • Ishihara Tohru ID: 9000403558963

    Articles in CiNii:1

    • Real-Time Power Management for a Multi-Performance Processor （2009）
  • Tohru Ishihara ID: 9000018481705

    Articles in CiNii:2

    • An Energy Optimization Framework for Embedded Applications （2011）
    • An Energy Optimization Framework for Embedded Applications （2011）
  • ISHIHARA TOHRU ID: 9000241456192

    Articles in CiNii:1

    • An Optimization Technique for Low-Energy Embedded Memory Systems (IPSJ Transactions on System LSI Design Methodology Vol.2) （2009）
  • ISHIHARA TOHRU ID: 9000241456270

    Articles in CiNii:1

    • Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion (IPSJ Transactions on System LSI Design Methodology Vol.2) （2009）
  • Tohru Ishihara ID: 9000404086279

    Articles in CiNii:1

    • A Process-Scheduler-Based Approach to Minimum Energy Point Tracking （2019）
  • Tohru Ishihara ID: 9000404307960

    Articles in CiNii:1

    • A Software Implementation of Minimum Energy Point Tracking Algorithm for Microprocessors （2018）
  • ISHIHARA TOHRU ID: 9000001483706

    Department of Surgery Shirahigebashi Hospital （1997 from CiNii）

    Articles in CiNii:1

    • Squamous Cell Carcinoma of the Pancreas Accompanied by Mucinous Cystadenocarcinoma : A Case Report of an Unusual Association （1997）
  • ISHIHARA TOHRU ID: 9000272644631

    Department of Communications and Computer Engineering Graduate School of Informatics, Kyoto University （2014 from CiNii）

    Articles in CiNii:1

    • Evaluation of Charge Scheduling on a Multi-Banked Supercapacitor Architecture for Energy Harvesting Embedded Systems （2014）
  • ISHIHARA TOHRU ID: 9000272645996

    Department of Communications and Computer Engineering Graduate School of Informatics, Kyoto University （2014 from CiNii）

    Articles in CiNii:1

    • Evaluation of Charge Scheduling on a Multi-Banked Supercapacitor Architecture for Energy Harvesting Embedded Systems （2014）
  • ISHIHARA Tohru ID: 1000030323471

    Articles in CiNii:108

    • A Reliability Evaluation Technique for Soft-Error Susceptible Computer Systems （2005）
    • A Code Placement Technique for Improving the Performance Yield of Processors with Defective Caches （2005）
    • A Reliability Evaluation Technique for Soft-Error Susceptible Computer Systems （2006）
  • ISHIHARA Tohru ID: 9000000413257

    Department of Bioscience and Biotechnology, Shinshu University （1997 from CiNii）

    Articles in CiNii:2

    • Purification and Characterization of Polyamine Aminotransferase of Arthrobacter sp. TMP-1^1 （1997）
    • Action of Polyamine Aminotransferase on Norspermidine （1997）
  • ISHIHARA Tohru ID: 9000004793373

    Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University （1999 from CiNii）

    Articles in CiNii:1

    • A Memory Power Optimization Technique for Application Specific Embedded Systems （1999）
  • ISHIHARA Tohru ID: 9000004797519

    VLSI Design and Education Center, the University of Tokyo （2001 from CiNii）

    Articles in CiNii:1

    • A System Level Optimization Technique for Application Specific Low Power Memories （2001）
  • ISHIHARA Tohru ID: 9000004820798

    Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering （2000 from CiNii）

    Articles in CiNii:1

    • System LSI Design Methods for Low Power LSIs （2000）
  • ISHIHARA Tohru ID: 9000004820837

    the Department of Computer Science and Communication Engineering, Kyushu University （2000 from CiNii）

    Articles in CiNii:1

    • A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection （2000）
  • ISHIHARA Tohru ID: 9000004848508

    Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University （1998 from CiNii）

    Articles in CiNii:1

    • Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches （1998）
  • ISHIHARA Tohru ID: 9000004874802

    The authors are with the Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering, Kyushu University （1998 from CiNii）

    Articles in CiNii:1

    • Programmable Power Management Architecture for Power Reduction （1998）
  • ISHIHARA Tohru ID: 9000005100757

    東京工業大学 （1992 from CiNii）

    Articles in CiNii:1

    • アフィン・スケーリング法に対するBigM法の適用(数理計画) （1992）
  • ISHIHARA Tohru ID: 9000005747442

    Graduate School of Engineering, Osaka University （1999 from CiNii）

    Articles in CiNii:1

    • Brillouin Scattering in Densified GeO_2 Glasses （1999）
  • ISHIHARA Tohru ID: 9000016498596

    System LSI Research Center, Kyushu University （2008 from CiNii）

    Articles in CiNii:2

    • Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems （2008）
    • Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems （2007）
  • 1 / 5
Page Top