Search Results1-20 of  54

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  • KAJIHARA SEIJI ID: 9000241439899

    Articles in CiNii:1

    • Delay Testing : Improving Test Quality and Avoiding Over-testing (LSI Design Methodology Vol.4) (2011)
  • KAJIHARA SEIJI ID: 9000241446797

    Articles in CiNii:1

    • On Delay Test Quality for Test Cubes (IPSJ Transactions on System LSI Design Methodology Vol.3) (2010)
  • KAJIHARA SEIJI ID: 9000241458542

    Articles in CiNii:1

    • Estimation of Delay Test Quality and Its Application to Test Generation (IPSJ Transactions on System LSI Design Methodology Vol.1) (2008)
  • KAJIHARA Seiji ID: 9000377384802

    Articles in CiNii:1

    • On Avoiding Test Data Corruption by Optimal Scan Chain Grouping (VLSI設計技術) -- (デザインガイア2017 : VLSI設計の新しい大地) (2017)
  • KAJIHARA Seiji ID: 9000377386290

    Articles in CiNii:1

    • On Avoiding Test Data Corruption by Optimal Scan Chain Grouping (ディペンダブルコンピューティング) -- (デザインガイア2017 : VLSI設計の新しい大地) (2017)
  • KAJIHARA Seiji ID: 1000080252592

    Computer Science and Systems Engineering, Kyushu Institute of Technology (2014 from CiNii)

    Articles in CiNii:175

    • Removal of Redundancy in Combinational Circuits by Classification of Undetectable Faults (1992)
    • On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume (2003)
    • Multiple Scan Tree Design for Test Compression (2003)
  • KAJIHARA Seiji ID: 9000004743436

    Graduate School of Computer Science and System Engineering, Kyushu Institute of Technology:Center for Microelectronics Systems, Kyushu Institute of Technology (2003 from CiNii)

    Articles in CiNii:1

    • Estimation of Fault Coverage in Path Delay Fault Testing (2003)
  • KAJIHARA Seiji ID: 9000004802053

    Faculty of Engineering, Osaka University (1995 from CiNii)

    Articles in CiNii:1

    • Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis (1995)
  • KAJIHARA Seiji ID: 9000004802104

    Faculty of Engineering, Osaka University (1995 from CiNii)

    Articles in CiNii:1

    • Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement (1995)
  • KAJIHARA Seiji ID: 9000006072260

    Kyushu Institute of Technology (2006 from CiNii)

    Articles in CiNii:1

    • A Statistical Quality Model for Delay Testing (2006)
  • KAJIHARA Seiji ID: 9000006500007

    Graduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology:Center for Microelectronics Systems, Kyushu Institute of technology (2002 from CiNii)

    Articles in CiNii:1

    • Average Power Reduction in Scan Testing by Test Vector Modification (2002)
  • KAJIHARA Seiji ID: 9000006500026

    Kyushu Insteitute oF Technology (2002 from CiNii)

    Articles in CiNii:1

    • Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan (2002)
  • KAJIHARA Seiji ID: 9000016492515

    Department of Computer Sciences and Electronics, Kyushu Institute of Technology (2006 from CiNii)

    Articles in CiNii:1

    • On Finding Don't Cares in Test Sequences for Sequential Circuits (2006)
  • KAJIHARA Seiji ID: 9000017681274

    Department of Computer Science and Electronics of Kyushu Institute of Technology (2008 from CiNii)

    Articles in CiNii:1

    • FOREWORD (2008)
  • KAJIHARA Seiji ID: 9000107314868

    Kyushu Institute of Technology (2011 from CiNii)

    Articles in CiNii:1

    • Capture Power Reduction in Multi-cycle Test Structure (2011)
  • KAJIHARA Seiji ID: 9000107317976

    Kyushu Institute of Technology (2011 from CiNii)

    Articles in CiNii:1

    • Capture Power Reduction in Multi-cycle Test Structure (2011)
  • KAJIHARA Seiji ID: 9000107319987

    Kyushu Institute of Technology (2012 from CiNii)

    Articles in CiNii:1

    • Pattern Merging for Additional Path Delay Fault Detection with Transition Delay Fault Test (2012)
  • KAJIHARA Seiji ID: 9000107321758

    Kyushu Institute of Technology (2008 from CiNii)

    Articles in CiNii:1

    • Transistor Aging and Operational Environment of Logic Circuits (2008)
  • KAJIHARA Seiji ID: 9000240076697

    Department of Computer Sciences and Electronics, Kyushu Institute of Technology (2013 from CiNii)

    Articles in CiNii:1

    • Scan-Out Power Reduction for Logic BIST (2013)
  • KAJIHARA Seiji ID: 9000240076705

    Kyushu Institute of Technology (2013 from CiNii)

    Articles in CiNii:1

    • A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing (2013)
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