Search Results1-20 of  99

  • 1 / 5
  • KAMEYAMA Michitaka ID: 9000002298092

    Graduate School of Information Sciences, Tohoku University (2012 from CiNii)

    Articles in CiNii:14

    • Architecture of a high-performance stereo vision VLSI processor (2000)
    • Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment (2008)
    • Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture (2009)
  • KAMEYAMA Michitaka ID: 9000004802183

    Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University (1995 from CiNii)

    Articles in CiNii:1

    • Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate (1995)
  • KAMEYAMA Michitaka ID: 9000004815756

    Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University (1997 from CiNii)

    Articles in CiNii:1

    • Design and Implementation of a Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control (1997)
  • KAMEYAMA Michitaka ID: 9000004815763

    Graduate School of Information Sciences, Tohoku University (1997 from CiNii)

    Articles in CiNii:1

    • Design and Evaluation of a 4-Valued Universal-Literal CAM for Cellular Logic Image Processing (1997)
  • KAMEYAMA Michitaka ID: 9000004819974

    Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University (1999 from CiNii)

    Articles in CiNii:1

    • Multiple-Valued Logic-in-Memory VLSI Architecture Based on Floating-Gate-MOS Pass-Transistor Logic (1999)
  • KAMEYAMA Michitaka ID: 9000004820049

    Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University (1999 from CiNii)

    Articles in CiNii:1

    • Collision Detection VLSI Processor for Intelligent Vehicles Using a Hierarchically-Content-Addressable Memory (1999)
  • KAMEYAMA Michitaka ID: 9000004836891

    Graduate School of Information Sciences, Tohoku University (2011 from CiNii)

    Articles in CiNii:7

    • Memory Allocation for Multi-Resolution Image Processing (2008)
    • Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture (2008)
    • A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals (2010)
  • KAMEYAMA Michitaka ID: 9000004840201

    Graduate School of Information Sciences, Tohoku University (2004 from CiNii)

    Articles in CiNii:1

    • Architecture of a Fine-Grain Field-Programmable VLSI Based on Multiple-Valued Source-Coupled Logic (2004)
  • KAMEYAMA Michitaka ID: 9000004976576

    Graduate School of Information Sciences, Tohoku University (2004 from CiNii)

    Articles in CiNii:1

    • Design and Evaluation of Fine-Grain Field-Programmable VLSI Based on Multiple-Valued Source-Coupled Logic (2004)
  • KAMEYAMA Michitaka ID: 9000004983684

    Graduate School of Information Sciences, Tohoku University (2003 from CiNii)

    Articles in CiNii:1

    • C-12-4 Low Power Field Programmable VLSI Processor Using Multiple Supply Voltages (2003)
  • KAMEYAMA Michitaka ID: 9000006179086

    Graduate School of Information Sciences, Tohoku University (2006 from CiNii)

    Articles in CiNii:1

    • Advanced VLSI Architecture for Intelligent Integrated Systems (2006)
  • KAMEYAMA Michitaka ID: 9000006205082

    Graduate School of Information Sciences, Tohoku University (2006 from CiNii)

    Articles in CiNii:1

    • Advanced VLSI Architecture for Intelligent Integrated Systems (2006)
  • KAMEYAMA Michitaka ID: 9000014662018

    Graduate School of Information Sciences, Tohoku University (2009 from CiNii)

    Articles in CiNii:1

    • Network Coding-Based Reliable Multicast Scheme in Wireless Networks (2009)
  • KAMEYAMA Michitaka ID: 9000016493971

    Graduate School of Information Sciences, Tohoku University (2006 from CiNii)

    Articles in CiNii:1

    • Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification (2006)
  • KAMEYAMA Michitaka ID: 9000016494074

    Graduate Shcool of Information Sciences, Tohoku University (2006 from CiNii)

    Articles in CiNii:1

    • A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates (2006)
  • KAMEYAMA Michitaka ID: 9000016498511

    Graduate School of Information Sciences, Tohoku University (2007 from CiNii)

    Articles in CiNii:1

    • FOREWORD (2007)
  • KAMEYAMA Michitaka ID: 9000017683335

    Graduate School of Information Sciences, Tohoku University (2008 from CiNii)

    Articles in CiNii:1

    • Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling (2008)
  • KAMEYAMA Michitaka ID: 9000017683667

    Graduate School of Information Science, Tohoku University (2008 from CiNii)

    Articles in CiNii:1

    • Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation (2008)
  • KAMEYAMA Michitaka ID: 9000017687881

    Graduate School of Information Science, Tohoku University (2010 from CiNii)

    Articles in CiNii:1

    • Group Testing Based Detection of Web Service DDoS Attackers (2010)
  • KAMEYAMA Michitaka ID: 9000018262768

    Faculty of Engineering, Tohoku University (1995 from CiNii)

    Articles in CiNii:1

    • Architecture and Performance Evaluation of a Model-Based Rodot Vision VLSI Processor for 3-D Instrumentation (1995)
  • 1 / 5
Page Top