Search Results1-18 of  18

  • Kotani Toshiya ID: 9000025083177

    Articles in CiNii:1

    • Full-chip layout optimization for process mar in enhancement using model-based hotspot fixing system (Special issue: Microprocesses and nanotechnology) (2010)
  • KOTANI Toshiya ID: 9000001729627

    Nonprofit Organization Green-Necklace (2009 from CiNii)

    Articles in CiNii:4

    • Continuous Grade Seoaration Project of Railway-Road and Urban Improvement along the Railway Area (2006)
    • Present circumstances and Future perspectives of City Planners (2007)
    • The Present Circumstances of City Planners from the Result of Questionnaire (2007)
  • KOTANI Toshiya ID: 9000004954195

    Toshiba Corporation Semiconductor & Storage Company (2014 from CiNii)

    Articles in CiNii:8

    • Layout Methodology for Self-Alinged Double Patterning (2011)
    • 65nm世代以降のリソフレンドリ設計技術 (2004)
    • 65nm世代以降のリソフレンドリ設計技術 (2004)
  • KOTANI Toshiya ID: 9000005546131

    Microelectronics Laboratory, Toshiba Corporation (1999 from CiNii)

    Articles in CiNii:3

    • Highly Accurate Process Proximity Correction Based on Empirical Model for 0.18 μm Generation and Beyond (1999)
    • Development of An Accurate Optical Proximity Correction System for 1 Gbit Dynamic Randam Access Memory Fabrication (1999)
    • TEM Observation of Dark Defects Appearing in InGaAsP/InP Double-Heterostructure Light Emitting Diodes Aged at High Temperature (1981)
  • KOTANI Toshiya ID: 9000014656120

    Articles in CiNii:1

    • Taming the Interdependent Preferences in Matching Protocols (2009)
  • KOTANI Toshiya ID: 9000019096088

    Toshiba Corporation (2011 from CiNii)

    Articles in CiNii:1

    • Layout Methodology for Self-Aligned Double Patterning (2011)
  • KOTANI Toshiya ID: 9000107317036

    Toshiba Corporation (2011 from CiNii)

    Articles in CiNii:1

    • Layout Methodology for Self-Alinged Double Patterning (2011)
  • KOTANI Toshiya ID: 9000107377833

    Process & Manufacturing Engineering Center, TOSHIBA CORPORATION Semiconductor Company (2003 from CiNii)

    Articles in CiNii:1

    • Optical Proximity Correction Feature Extraction Method Using Reticle Scanning Electron Microscope Images (2003)
  • Kotani Toshiya ID: 9000054744207

    Articles in CiNii:1

    • Tolerance-Based Wafer Verification Methodologies with a Die-to-Database Inspection System (2009)
  • Kotani Toshiya ID: 9000254403557

    埼玉大学 (1991 from CiNii)

    Articles in CiNii:1

    • A Study on the Transitions of Landscape Structure around the Imperial Palace (1991)
  • Kotani Toshiya ID: 9000254403606

    (株) 都市計画設計研究所 (1993 from CiNii)

    Articles in CiNii:1

    • A Study on the Transition of Spatial Structure in Samurai's Living Quarters (1993)
  • Kotani Toshiya ID: 9000254940175

    埼玉大学大学院 (1992 from CiNii)

    Articles in CiNii:1

    • A Study on the Historical Transition of Concealed Open Space around the Imperial Palac (1992)
  • Kotani Toshiya ID: 9000254940521

    (株) 都市計面設計研究所 (1996 from CiNii)

    Articles in CiNii:1

    • A Study On the Transison of Spatial Structure Where the Hiroshima City was born (1996)
  • Kotani Toshiya ID: 9000401683665

    Articles in CiNii:1

    • Development of An Accurate Optical Proximity Correction System for 1 Gbit Dynamic Random Access Memory Fabrication (1999)
  • Kotani Toshiya ID: 9000401684457

    Articles in CiNii:1

    • 1999-12-30 (1999)
  • Kotani Toshiya ID: 9000401717121

    Articles in CiNii:1

    • Optical Proximity Correction Feature Extraction Method Using Reticle Scanning Electron Microscope Images (2003)
  • Kotani Toshiya ID: 9000401788712

    Articles in CiNii:1

    • Full-Chip Layout Optimization for Process Margin Enhancement Using Model-Based Hotspot Fixing System (2010)
  • Kotani Toshiya ID: 9000403547414

    Articles in CiNii:1

    • 2000-04-01 (2000)
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