Search Results1-12 of  12

  • KUMASHIRO Shigetaka ID: 9000001718617

    ULSI Device Development Laboratories, NEC Corporation (1998 from CiNii)

    Articles in CiNii:1

    • A Precise SOI Film Thickness Measurement Including Gate Depletion and Quantum Effects (1998)
  • KUMASHIRO Shigetaka ID: 9000004777930

    MIRAI-Selete (2009 from CiNii)

    Articles in CiNii:16

    • Process simulation : Ion implantation (2003)
    • Development of a Universal Diffusion Scheme for a Two-Dimensional Process Simulator (1997)
    • A Three-Dimensional Interconcect Simulator with a Robast Delauney Terrahedral Partitioning Algorithm (1993)
  • KUMASHIRO Shigetaka ID: 9000004822077

    MIRAI-Selete (2012 from CiNii)

    Articles in CiNii:10

    • MOSFET Harmonic Distortion up to the Cutoff Frequency : Measurement and Theoretical Analysis (2005)
    • A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits (2011)
    • On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement (2011)
  • KUMASHIRO Shigetaka ID: 9000004875016

    the ULSI Device Development Laboratories, NEC Corporation (1999 from CiNii)

    Articles in CiNii:1

    • Modeling of Channel Boron Distribution in Deep Sub-0.1μm n-MOSFETs (1999)
  • KUMASHIRO Shigetaka ID: 9000004897385

    NEC Electron Devices, NEC Corporation (2000 from CiNii)

    Articles in CiNii:3

    • Novel Simulation Technology for Semiconductor Device[II] : Simulation Technology of Fine CMOS-2 ; Simulation of Non-equilibrium Carrier Transport in CMOS Devices (1999)
    • Simulation Technology of CMOS Process and Device (2000)
    • Novel Simulation Technology for Semiconductor Device [1] : Simulation Technology of Fine CMOS-1; Accuracy Improvement of CMOS Device Simulation (1999)
  • KUMASHIRO Shigetaka ID: 9000017683578

    MIRAI-Selete (2008 from CiNii)

    Articles in CiNii:1

    • Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress (2008)
  • KUMASHIRO Shigetaka ID: 9000018426385

    MIRAI-Selete (2010 from CiNii)

    Articles in CiNii:1

    • Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns (2010)
  • KUMASHIRO Shigetaka ID: 9000263066030

    MIRAI-Selete (2013 from CiNii)

    Articles in CiNii:1

    • Measurements and Simulation Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation (2013)
  • Kumashiro Shigetaka ID: 9000004872167

    the ULSI Device Development Laboratories, NEC Corporation (1994 from CiNii)

    Articles in CiNii:1

    • Efficient Transient Device Simulation with AWE Macromodels and Domain Decomposition (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD93)) (1994)
  • Kumashiro Shigetaka ID: 9000258161032

    Semiconductor Technology Academic Research Center, 3-17-2, Shin-Yokohama, Kanagawa 222-0033, Japan (2002 from CiNii)

    Articles in CiNii:1

    • Quantum Effect in Sub-0.1 .MU.m MOSFET with Pocket Technologies and Its Relevance for the On-Current Condition. (2002)
  • Kumashiro Shigetaka ID: 9000401705980

    Articles in CiNii:1

    • 2002-04-30 (2002)
  • Kumashiro Shigetaka ID: 9000401757910

    Articles in CiNii:1

    • 2007-04-24 (2007)
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