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  • KAMO Atsushi ID: 9000002536245

    Sony LSI Design Inc. (2003 from CiNii)

    Articles in CiNii:22

    • Study of Optimal Placement Method for Decoupling Capacitors on Printed Circuit Board (2001)
    • Efficient Techniques of Macromodel Synthesis for Interconnects and Electromagnetic Emissions Using FDTD Method (2001)
    • Steady-State Analysis of MOS Circuits by Shooting Method Based on Decomposition Techniques (1998)
  • KAMO Atsushi ID: 9000004792798

    Sony LSI Design Inc. (2004 from CiNii)

    Articles in CiNii:7

    • A Fast Algorithm for spatiotemporal Pattern Analysis of Neural Networks with Multivalued Logic (1998)
    • Transient Analysis for Transmission Line Networks Using Expanded GMC (1999)
    • A Fast Neural Network Simulator for State Transition Analysis (1999)
  • KAMO Atsushi ID: 9000004850453

    Department of Systems Engineering, Faculty of Engineering, Shizuoka University (2002 from CiNii)

    Articles in CiNii:1

    • A Novel Application of Verilog-A to Modeling and Simulation of High-Speed Interconnects in Time/Frequency Transform-Domain (2002)
  • Kamo Atsushi ID: 9000258391470

    Sony LSI Design Inc. (2003 from CiNii)

    Articles in CiNii:1

    • Time Domain Circuit Simulation Using Nonlinear Reduction Technique (2003)
  • Kamo Atsushi ID: 9000391795932

    Shizuoka Univ. Graduate school of electronic science and technology (2002 from CiNii)

    Articles in CiNii:1

    • On the Notes of Optimal Location for Decoupling Capacitors on PCB Using Poynting Vectors (2002)
  • Kamo Atsushi ID: 9000391795936

    Shizuoka Univ. Graduate school of electronic science and technology (2002 from CiNii)

    Articles in CiNii:1

    • An high-speed simulator based on model reduction technique (2002)
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