Search Results1-5 of  5

  • MOROOKA Yoshikazu ID: 9000000494576

    the ULSI Laboratory, Mitsubishi Electric Corporation (1996 from CiNii)

    Articles in CiNii:1

    • Cell-Plate-Line/Bit-Line Complementary Sensing (CBCS) Architecture for Ultra Low-Power DRAM's (1996)
  • MOROOKA Yoshikazu ID: 9000004779265

    Articles in CiNii:4

    • 混載DRAM用モジュールジェネレータ (特集「半導体」) (2002)
    • A Delay-Locked Loop and 90-degree Phase Shifter for 800Mbps Double Data Rate Memories (1998)
    • A Delay-Locked Loop and 90-degree Phase Shifter for 800Mbps Double Data Rate Memories (1998)
  • MOROOKA Yoshikazu ID: 9000004811966

    the ULSI Laboratory, Mitsubishi Electric Corporation (1996 from CiNii)

    Articles in CiNii:3

    • A Low Power and High Speed Data Transfer Scheme with Asynchronous Compressed Pluse Width Modulation for AS-Memory (1996)
    • Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs (1995)
    • An Efficient Back-Bias Generator with Hybrid Pumping Circuit for 1.5-V DRAM's (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994)) (1994)
  • MOROOKA Yoshikazu ID: 9000004826221

    Renesas Technology (2009 from CiNii)

    Articles in CiNii:3

    • A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test (2009)
    • A 0.18μm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller (2002)
    • An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester (2003)
  • MOROOKA Yoshikazu ID: 9000004966362

    ULSI Laboratory, Mitsubishi Electric Corp. (1995 from CiNii)

    Articles in CiNii:1

    • Cell-Plate-Line/Bit-Line Complementary Sensing (CBCS) Architecture for Ultra Low-Power DRAMs (1995)
Page Top