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  • MURAI Yasumitsu ID: 9000004974048

    Renesas Design Corporation (2007 from CiNii)

    Articles in CiNii:6

    • Improvement of input characteristic using SSTL_3 interface (1997)
    • A 180 MHz multiple-registered 16 Mbit synchronous DRAM (1994)
    • 16M bit Synchronous DRAM with 64 bit data compressed Test Mode (1994)
  • MURAI Yasumitsu ID: 9000402240473

    Renesas Electronics Corporation (2019 from CiNii)

    Articles in CiNii:1

    • A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications (2019)
  • Murai Yasumitsu ID: 9000004871041

    the LSI Design Center, Mitsubishi Elecoric Engineering Company Limited (1994 from CiNii)

    Articles in CiNii:2

    • A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories (Special Issue on LSI Memories) (1993)
    • A Flexible Search Managing Circuitry for High-Density Dynamic CAMs (Speial Section on High Speed and High Density Multi Functional LSI Memories) (1994)
  • Murai Yasumitsu ID: 9000004873051

    Mitsubishi Electric Engineering Company Ltd., (1994 from CiNii)

    Articles in CiNii:1

    • A 180 MHz Multiple-Registered 16 Mbit SDRAM with Flexible Timing Scheme (Special Section on High Speed and High Density Multi Functional LSI Memories) (1994)
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