Search Results1-4 of  4

  • NAKASHIMA Hidenari ID: 9000005818154

    NEC Electronics Corp. (2010 from CiNii)

    Articles in CiNii:8

    • Optimization Technique of Number of Interconnect Layers and Circuit Area Based on Wire Length Distribution (2004)
    • Impact of Self-Heating in Wire Interconnection on Timing (2010)
    • Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations (2009)
  • NAKASHIMA Hidenari ID: 9000016259949

    NEC Electronics Corp. (2007 from CiNii)

    Articles in CiNii:1

    • Fast Methods to Estimate Clock Jitter due to Power Supply Noise (2007)
  • Nakashima Hidenari ID: 9000004929434

    Precision and Intelligence Laboratory, Tokyo Institute of Technology (2004 from CiNii)

    Articles in CiNii:2

    • A-3-21 Optimization of Interconnect Structure for 65nm Process Based on Interconnect Length Distribution (2004)
    • ULSI Interconnect Length Distribution Using Core Utilization (2003)
  • Nakashima Hidenari ID: 9000024957810

    Articles in CiNii:1

    • Optimization Methodology of Layer Numbers with Circuit/Process Co-Design (2006)
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