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  • NAKASHIMA YASUHIKO ID: 9000344831966

    Articles in CiNii:1

    • A Framework for Tree-based Checkpointing Architecture on FPGAs (VLSI設計技術) (2017)
  • NAKASHIMA YASUHIKO ID: 9000344833119

    Articles in CiNii:1

    • A Framework for Tree-based Checkpointing Architecture on FPGAs (コンピュータシステム) (2017)
  • NAKASHIMA YASUHIKO ID: 9000344835663

    Articles in CiNii:1

    • A Framework for Tree-based Checkpointing Architecture on FPGAs (リコンフィギャラブルシステム) (2017)
  • NAKASHIMA Yasuhiko ID: 9000356884103

    Articles in CiNii:1

    • A Compact Low-Latency Systematic Successive Cancellation Polar Decoder for Visible Light Communication Systems (コンピュータシステム) (2017)
  • NAKASHIMA Yasuhiko ID: 9000356884171

    Articles in CiNii:1

    • A prototype of Dimmable Visible Light Communication System on FPGA (コンピュータシステム) (2017)
  • NAKASHIMA Yasuhiko ID: 9000356885658

    Articles in CiNii:1

    • A Compact Low-Latency Systematic Successive Cancellation Polar Decoder for Visible Light Communication Systems (ディペンダブルコンピューティング) (2017)
  • NAKASHIMA Yasuhiko ID: 9000356885670

    Articles in CiNii:1

    • A prototype of Dimmable Visible Light Communication System on FPGA (ディペンダブルコンピューティング) (2017)
  • NAKASHIMA Yasuhiko ID: 9000363904823

    Articles in CiNii:1

    • An IoT Monitoring Prototype System for Smart Farm Using Zigbee and Raspberry Pi Module (無線通信システム) (2017)
  • NAKASHIMA YASUHIKO ID: 1000000314170

    Articles in CiNii:126

    • 胆汁酸塩,牛胆酸等に依る結核海〓の治療実験 (1960)
    • モルモットにおける実験的結核の研究-1・2- (1960)
    • Improvement of FU Array Accelerator by Time Division Execution (2012)
  • NAKASHIMA YASUHIKO ID: 9000272646384

    Computing Architecture Lab, Graduate School of Information Science, Nara Institute of Science and Technology (2014 from CiNii)

    Articles in CiNii:1

    • An Asynchronous Commit DMR Architecture for Aggressive Low-Power Fault Toleration (2014)
  • NAKASHIMA Yasuhiko ID: 9000240076602

    Graduate School of Information Science, Nara Institute of Science and Technology (2013 from CiNii)

    Articles in CiNii:1

    • Selective Check of Data-Path for Effective Fault Tolerance (2013)
  • NAKASHIMA Yasuhiko ID: 9000283335844

    Graduate School of Information Science, Nara Institute of Science and Technology (2014 from CiNii)

    Articles in CiNii:1

    • Understanding Variations for Better Adjusting Parallel Supplemental Redundant Executions to Tolerate Timing Faults (2014)
  • NAKASHIMA Yasuhiko ID: 9000283335846

    Nara Institute of Science and Technology (2014 from CiNii)

    Articles in CiNii:1

    • A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction (2014)
  • NAKASHIMA Yasuhiko ID: 9000311504903

    Nara Institute of Science and Technology (NAIST) (2015 from CiNii)

    Articles in CiNii:1

    • FOREWORD (2015)
  • NAKASHIMA Yasuhiko ID: 9000311504943

    Graduate School of Information Science, Nara Institute of Science and Technology (2015 from CiNii)

    Articles in CiNii:1

    • Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators (2015)
  • NAKASHIMA Yasuhiko ID: 9000345196511

    Computing Architecture Lab, Graduate School of Information Science, Nara Institute of Science and Technology (2016 from CiNii)

    Articles in CiNii:1

    • Performance Optimization of Light-Field Applications on GPU (2016)
  • NAKASHIMA Yasuhiko ID: 9000380977407

    Nara Institute of Science and Technology (2018 from CiNii)

    Articles in CiNii:1

    • A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing (2018)
  • NAKASHIMA Yasuhiko ID: 9000399238745

    Graduate School of Information Science, Nara Institute of Science and Technology (2018 from CiNii)

    Articles in CiNii:1

    • Log-Likelihood Ratio Calculation Using 3-Bit Soft-Decision for Error Correction in Visible Light Communication Systems (2018)
  • NAKASHIMA Yasuhiko ID: 9000403156772

    Nara Institute of Science and Technology (2019 from CiNii)

    Articles in CiNii:1

    • Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation (2019)
  • NAKASHIMA Yasuhiko ID: 9000403158449

    Graduate School of Information Science, Nara Institute of Science and Technology (2019 from CiNii)

    Articles in CiNii:1

    • A ReRAM-Based Row-Column-Oriented Memory Architecture for Convolutional Neural Networks (2019)
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