Search Results1-12 of  12

  • Narihiro Mitsuru ID: 9000024979856

    Articles in CiNii:1

    • Interfacial atomic structure between Pt-added NiSi and Si(001) (Special issue: Solid state devices and materials) (2011)
  • NARIHIRO Mitsuru ID: 9000004964808

    Renesas Electronics Corporation (2014 from CiNii)

    Articles in CiNii:7

    • A 65nm-node interconnect technology using ultra-thin low-k pore seal (2004)
    • Low Cost and Highly Reliable, 65nm-node Cu Dual Damascene Interconnects (2004)
    • Impact of Radical Oxynitridation on Characteristics & Reliability of Sub-1.5nm-Thick Gate-Dielectric FETs with Narrow Channel and Shallow Trench Isolation (2002)
  • NARIHIRO Mitsuru ID: 9000005845013

    System Devices Research Laboratories, NEC Corporation (2005 from CiNii)

    Articles in CiNii:3

    • Estimation of Optimum Electron-Beam Projection Lithography Mask Biases Taking Coulomb Beam Blur into Consideration (2003)
    • 10-nm-Scale Pattern Delineation Using Calixarene Electron Beam Resist for Complementary Metal Oxide Semiconductor Gate Etching (2005)
    • Intra-Level Mix-and-Match Lithography Process for Fabricating Sub-100-nm Complementary Metal-Oxide-Semiconductor Devices using the JBX-9300FS Point-Electron-Beam System (2000)
  • Narihiro Mitsuru ID: 9000258149691

    System Devices and Fundamental Research, NEC Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan (2000 from CiNii)

    Articles in CiNii:1

    • Intra-Level Mix-and-Match Lithography Process for Fabricating Sub-100-nm Complementary Metal-Oxide-Semiconductor Devices using the JBX-9300FS Point-Electron-Beam System. (2000)
  • Narihiro Mitsuru ID: 9000258183896

    System Devices Research Laboratories, NEC Corporation (2005 from CiNii)

    Articles in CiNii:1

    • 10-nm-Scale Pattern Delineation Using Calixarene Electron Beam Resist for Complementary Metal Oxide Semiconductor Gate Etching (2005)
  • Narihiro Mitsuru ID: 9000401692908

    Articles in CiNii:1

    • Intra-Level Mix-and-Match Lithography Process for Fabricating Sub-100-nm Complementary Metal-Oxide-Semiconductor Devices using the JBX-9300FS Point-Electron-Beam System (2000)
  • Narihiro Mitsuru ID: 9000401716977

    Articles in CiNii:1

    • Estimation of Optimum Electron-Beam Projection Lithography Mask Biases Taking Coulomb Beam Blur into Consideration (2003)
  • Narihiro Mitsuru ID: 9000401739342

    Articles in CiNii:1

    • 10-nm-Scale Pattern Delineation Using Calixarene Electron Beam Resist for Complementary Metal Oxide Semiconductor Gate Etching (2005)
  • Narihiro Mitsuru ID: 9000401795614

    Articles in CiNii:1

    • Interfacial Atomic Structure Between Pt-Added NiSi and Si(001) (2011)
  • Narihiro Mitsuru ID: 9000401808554

    Articles in CiNii:1

    • Effects of Low-$k$ Stack Structure on Performance of Complementary Metal Oxide Semiconductor Devices and Chip Package Interaction Failure (2012)
  • Narihiro Mitsuru ID: 9000401996489

    Articles in CiNii:1

    • Interfacial Atomic Structure Between Pt-Added NiSi and Si(001) (2011)
  • Narihiro Mitsuru ID: 9000402009413

    Articles in CiNii:1

    • Effects of Low-kStack Structure on Performance of Complementary Metal Oxide Semiconductor Devices and Chip Package Interaction Failure (2012)
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