Search Results1-20 of  31

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  • Nii Koji ID: 9000241499715

    Articles in CiNii:1

    • False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation (Special Issue : Solid State Devices and Materials) (2013)
  • NII Koji ID: 9000004820856

    Renesas Technology Corporation (2008 from CiNii)

    Articles in CiNii:5

    • A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology (2008)
    • A CAD-Compatible SOI-CMOS Gate Array Using 0.35μm Partially-Depleted Transistors (2000)
    • Realistic Scaling Scenario for Sub-100 nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation (2003)
  • NII Koji ID: 9000004930000

    System LSI Laboratory, Mitsubishi Electric Corporation (1997 from CiNii)

    Articles in CiNii:1

    • A High Speed SRAM memory cell for Low Voltage Gate Arrays (1997)
  • NII Koji ID: 9000004954736

    Articles in CiNii:85

    • Realization of Low-Power Dual-Port SRAM in 90 nm CMOS Technology with Self-Adjustable Sense-enable Generator Using Replica Ciruit (2003)
    • Comparison of the Interconnect Capacitances for Various SRAM Cell Layouts to Achieve High-Speed and Low-Power Memory Cell (2003)
    • Impact of Actively Body-bias Controlled (ABC) SOI SRAM for Low-Voltage and High-Speed Operation (2004)
  • NII Koji ID: 9000016489203

    Kobe University (2008 from CiNii)

    Articles in CiNii:4

    • A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing (2008)
    • A 0.3-V Operating, V_<th>-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond (2006)
    • Area Comparison between 6T and 8T SRAM Cells in Dual-V_<dd> Scheme and DVS Scheme (2007)
  • NII Koji ID: 9000017683683

    Renesas Technology Corporation (2008 from CiNii)

    Articles in CiNii:1

    • Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration (2008)
  • NII Koji ID: 9000019238042

    Renesas Electronics Corporation (2012 from CiNii)

    Articles in CiNii:1

    • Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation (2012)
  • NII Koji ID: 9000107316977

    Renesas Electronics Corporation (2011 from CiNii)

    Articles in CiNii:1

    • Immunity Evaluation of SRAM Core Using DPI with On-Chip Diagnosis Structures (2011)
  • NII Koji ID: 9000107359598

    Renesas Electronics Corporation (2011 from CiNii)

    Articles in CiNii:1

    • Immunity Evaluation of SRAM Core Using DPI with On-Chip Diagnosis Structures (2011)
  • NII Koji ID: 9000107378522

    Articles in CiNii:1

    • Challenging for an ultra low-voltage SRAM by innovative design circuits and device technologies : A 0.5V 100MHz PD-SOI SRAM using Asymmetric MOSFET and Forward Body Bias (2010)
  • NII Koji ID: 9000240075674

    Renesas Electronics Corporation (2013 from CiNii)

    Articles in CiNii:1

    • Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout (2013)
  • NII Koji ID: 9000240538846

    Renesas Electronics Corporation (2012 from CiNii)

    Articles in CiNii:1

    • Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process (2012)
  • NII Koji ID: 9000242566662

    Renesas Electronics Corporation (2013 from CiNii)

    Articles in CiNii:1

    • 4.5 Fine Grain Assist Bias Controlled SRAM(4. Variations in Device Characteristics,<Special Survey>Dependable VLSI System) (2013)
  • NII Koji ID: 9000242566735

    Renesas Electronics Corporation (2013 from CiNii)

    Articles in CiNii:1

    • 8.5 Physical Unclonable Functions : Memory PUF(8. Security,<Special Survey>Dependable VLSI System) (2013)
  • NII Koji ID: 9000243892886

    Renesas Electronics Corporation (2014 from CiNii)

    Articles in CiNii:1

    • A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation (2014)
  • NII Koji ID: 9000251015823

    Renesas Electronics Corporation (2013 from CiNii)

    Articles in CiNii:1

    • A 123μW Standby Power Technique with EM-Tolerant 1.8V I/O NMOS Power Switch in 28nm HKMG Technology (2013)
  • NII Koji ID: 9000251015871

    Renesas Electronics Corporation (2013 from CiNii)

    Articles in CiNii:1

    • A single chip LTE capable communication processor R-Mobile U2 and its technologies in power management : Clock control method by the "power saver" (2013)
  • NII Koji ID: 9000345259864

    Renesas Electronics Corporation|Graduate School of Natural Science & Technology, Kanazawa University (2016 from CiNii)

    Articles in CiNii:1

    • A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor (2016)
  • NII Koji ID: 9000402240476

    Renesas Electronics Corporation|Kanazawa University (2019 from CiNii)

    Articles in CiNii:1

    • A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications (2019)
  • Nii Koji ID: 9000019979441

    Articles in CiNii:1

    • Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential (2011)
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