Search Results1-20 of  22

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  • OHHATA Kenichi ID: 9000004813174

    Hitachi Device Engineering Co., Ltd. (1998 from CiNii)

    Articles in CiNii:5

    • Redundancy Circuit for a Sub-nanosecond, Megabit ECL-CMOS SRAM (1996)
    • Design of a 2 - ns Cycle Time 72 - kb ECL - CMOS SRAM Macro (1998)
    • Redundancy Technique for Ultra-High-Speed Static RAMs (1993)
  • OHHATA Kenichi ID: 9000006073391

    the Dept. of Electrical and Electronic Engineering, Kagoshima Univ. (2006 from CiNii)

    Articles in CiNii:1

    • Design of Low-Noise, Low-Power 10-GHz VCO Using 0.18-μm CMOS Technology (2006)
  • OHHATA Kenichi ID: 9000017685093

    Kagoshima University (2008 from CiNii)

    Articles in CiNii:1

    • Sandwich Structure Type RF-MEMS Variable Capacitor with Low Voltage Controllability and Wide Tuning Range (2008)
  • OHHATA Kenichi ID: 9000018708141

    Kagoshima University (2012 from CiNii)

    Articles in CiNii:52

    • Bandwidth enhancement technique for transimpedance amplifier using negative impedance circuit (2009)
    • A 90-nm CMOS 4×10Gb/s VCSEL Driver using Asymmetric Emphasis Technique for Optical Interconnection (2009)
    • Technique for improving power supply rejection ratio in transimpedance amplifier design (2012)
  • OHHATA Kenichi ID: 9000019135505

    the Department of Electrical and Elecironics Engineering, Kagoshima University (2011 from CiNii)

    Articles in CiNii:1

    • Low-Offset, Low-Power Latched Comparator Using Capacitive Averaging Technique (2011)
  • OHHATA Kenichi ID: 9000243892911

    Kagoshima University (2014 from CiNii)

    Articles in CiNii:1

    • 1-GHz, 17.5-mW, 8-bit Subranging ADC Using Offset-Cancelling Charge-Steering Amplifier (2014)
  • OHHATA Kenichi ID: 9000244924816

    Dept. of Electrical and Electronics Engineering, Kagoshima University (2013 from CiNii)

    Articles in CiNii:4

    • 1-GHz, 8-bit Subranging ADC(1) : Low-power techniques (2013)
    • 1-GHz, 8-bit Subranging ADC(2) : Experimental results and failure analysis (2013)
    • Automatic distortion compensation technique in resistor ladder for high-speed and low-power ADC (2013)
  • OHHATA Kenichi ID: 9000262058016

    Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University (2014 from CiNii)

    Articles in CiNii:1

    • C-12-8 Automatic distortion compensation technique in resistor ladder for high-speed and low-power ADC (2014)
  • OHHATA Kenichi ID: 9000262058136

    Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University (2014 from CiNii)

    Articles in CiNii:1

    • C-12-41 Power Reduction Technique for Clock Bootstrap Circuit (2014)
  • OHHATA Kenichi ID: 9000280546520

    Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University (2014 from CiNii)

    Articles in CiNii:1

    • C-12-13 Design of 300-MS/s, 8-bit, Two-Step Single Slope ADC (2014)
  • OHHATA Kenichi ID: 9000280546522

    Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University (2014 from CiNii)

    Articles in CiNii:1

    • C-12-14 Low Energy Comparator Using Temporal Boost Technique (2014)
  • OHHATA Kenichi ID: 9000301386621

    Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University (2015 from CiNii)

    Articles in CiNii:1

    • C-12-32 A 0.5-V, 1.2-GHz, 6-bit Flash ADC Using Temporal-Boost Comparator (2015)
  • Ohhata Kenichi ID: 9000021311980

    Kagoshima University (2008 from CiNii)

    Articles in CiNii:1

    • Feedthrough reduction technique for track-and-hold circuit with body-bias control circuit (2008)
  • Ohhata Kenichi ID: 9000021440168

    Kagoshima University (2007 from CiNii)

    Articles in CiNii:1

    • A 1-GHz, 56.3-dB SFDR CMOS track-and-hold circuit with body-bias control circuit (2007)
  • Ohhata Kenichi ID: 9000045921331

    Kagoshima University (2005 from CiNii)

    Articles in CiNii:1

    • B-13-21 An Investigation of method of connecting Sensor in Fiber-Optic Disaster Prevention System using FBGs (2005)
  • Ohhata Kenichi ID: 9000242894183

    Dept. of Electrical and Electronics Engineering, Kagoshima University (2013 from CiNii)

    Articles in CiNii:1

    • Comparator Topology Suited for Low-Voltage Operation (2013)
  • Ohhata Kenichi ID: 9000257865393

    Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University (2014 from CiNii)

    Articles in CiNii:1

    • Automatic technique of distortion compensation in resistor ladder for high-speed and low-power ADC (2014)
  • Ohhata Kenichi ID: 9000258452574

    Kagoshima University (2005 from CiNii)

    Articles in CiNii:1

    • An Investigation of Fiber-Optic Disaster Prevention System simulator using FBGs (2005)
  • Ohhata Kenichi ID: 9000311494897

    Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University (2015 from CiNii)

    Articles in CiNii:1

    • C-12-29 Design of 500-MS/s, 8-bit, Two-Step Single Slope ADC (2015)
  • Ohhata Kenichi ID: 9000311494909

    Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University (2015 from CiNii)

    Articles in CiNii:1

    • C-12-33 Performance comparison of low-voltage comparators (2015)
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