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  • SHIRATAKE Shinichiro ID: 9000004815158

    Microelectronics Engineering Laboratory, Toshiba Corporation (1997 from CiNii)

    Articles in CiNii:1

    • Folded Bitline Architecture for a Gigabit-Scale NAND DRAM (1997)
  • SHIRATAKE Shinichiro ID: 9000004964457

    Center for Semiconductor Research & Development, Semiconductor Company, Toshiba Corporation (2009 from CiNii)

    Articles in CiNii:9

    • An H.264/MPEG-4 Audio/Visual Codec LSI with Module-Wise Dynamic Voltage/Frequency Scaling (2005)
    • Bitline/Plateline Reference-Level-Precharge Scheme for High-Density ChainFeRAM (2003)
    • A dual layer bitline DRAM array for multi-gigabit DRAMs with cross point type cell (1996)
  • SHIRATAKE Shinichiro ID: 9000006072150

    Toshiba Corporation (2006 from CiNii)

    Articles in CiNii:1

    • Module-Wise Dynamic Voltage and Frequency Scaling for a 90nm H.264/MPEG-4 Codec LSI (2006)
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