Search Results1-20 of  68

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  • SUEYOSHI TOSHINORI ID: 9000004375519

    Kumamoto University (2009 from CiNii)

    Articles in CiNii:11

    • Inter - PE Communication Subsystem of the Kyushu University Reconfigurable Parallel Processor (1989)
    • A Distributed Operating System for a Reconfigurable Parallel Processor (1989)
    • Network Architecture of a Reconfigurable Parallel-Processor (1988)
  • SUEYOSHI TOSHINORI ID: 9000006575977

    Articles in CiNii:9

    • DDoS Detection Technique using Statistical Analysys considering Response Time (2010)
    • DDoS Detection Technique using Statistical Analysys considering Response Time (2010)
    • DDoS detection technique using statistical analysys considering response time (2010)
  • SUEYOSHI TOSHINORI ID: 9000290553937

    Graduate School of Science and Technology, Kumamoto University (2014 from CiNii)

    Articles in CiNii:1

    • Generalized Correspondence of Synchronous Circuit and State Machine using Category Theory (2014)
  • SUEYOSHI Toshinori ID: 1000000117136

    熊本大学大学院自然科学研究科 (2015 from CiNii)

    Articles in CiNii:263

    • Configurable Computing (1998)
    • A Study on Resource Sharing Technique for Multi-Context Logic Device (2006)
    • Implementation and Evaluation of Remote Logic Analyzer (2006)
  • SUEYOSHI Toshinori ID: 9000004804108

    Department of Artificial Intelligence, Kyushu Institute of Technology (1997 from CiNii)

    Articles in CiNii:1

    • A High-Performance Cluster Computing Environment Based on Hybrid Shared Memory/Message Passing Model (1997)
  • SUEYOSHI Toshinori ID: 9000004835614

    Kumamoto University (2004 from CiNii)

    Articles in CiNii:1

    • Special Section on Reconfigurable Systems (2004)
  • SUEYOSHI Toshinori ID: 9000004850654

    Department of Computer Science, Faculty of Engineering, Kumamoto University (2002 from CiNii)

    Articles in CiNii:1

    • Configurable and Reconfigurable Computing for Digital Signal Processing (2002)
  • SUEYOSHI Toshinori ID: 9000016493241

    Computer Science and Electrical Engineering in the Graduate School of Science and Technology at Kumamoto University (2007 from CiNii)

    Articles in CiNii:1

    • FOREWORD (2007)
  • SUEYOSHI Toshinori ID: 9000016493283

    Graduate School of Science and Technology, Kumamoto University (2012 from CiNii)

    Articles in CiNii:5

    • A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells (2011)
    • COGRE : A Novel Compact Logic Cell Architecture for Area Minimization (2012)
    • An Easily Testable Routing Architecture and Prototype Chip (2012)
  • SUEYOSHI Toshinori ID: 9000016656667

    Kumamoto University Graduate School of Science and Technology (2009 from CiNii)

    Articles in CiNii:1

    • ^1H MR Spectroscopy of Small Breast Tumors using Lipid Suppression at 1.5T (2009)
  • SUEYOSHI Toshinori ID: 9000107324747

    Articles in CiNii:1

    • A Case Study of Functionally-Distributed Dual Processor System on an FPGA (2009)
  • SUEYOSHI Toshinori ID: 9000240076597

    Graduate School of Science and Technology, Kumamoto University (2013 from CiNii)

    Articles in CiNii:1

    • FPGA Design Framework Combined with Commercial VLSI CAD (2013)
  • SUEYOSHI Toshinori ID: 9000242566699

    Kumamoto University (2013 from CiNii)

    Articles in CiNii:1

    • 6.4 Reliability Issues in 3D-LSI(6. Connectivity,<Special Survey>Dependable VLSI System) (2013)
  • SUEYOSHI Toshinori ID: 9000242652072

    Graduate School of Science and Technology Kumamoto University (2012 from CiNii)

    Articles in CiNii:1

    • A Design Framework for Reconfigurable IPs with VLSI CADs (2012)
  • SUEYOSHI Toshinori ID: 9000258734385

    the Graduate School of Science and Technology, Kumamoto University (2012 from CiNii)

    Articles in CiNii:1

    • Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration (2012)
  • SUEYOSHI Toshinori ID: 9000283336022

    Graduate School of Science and Technology, Kumamoto University (2015 from CiNii)

    Articles in CiNii:1

    • Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC (2015)
  • SUEYOSHI Toshinori ID: 9000305590079

    Graduate School of Science and Technology, Kumamoto University (2014 from CiNii)

    Articles in CiNii:1

    • Formal Verification System of Multi-clock Synchronous Circuits on Multimodal Logic (2014)
  • SUEYOSHI Toshinori ID: 9000308048670

    Graduate School of Science and Technology, Kumamoto University (2014 from CiNii)

    Articles in CiNii:1

    • A hardware description method and semantics providing a timing constraint (2014)
  • SUEYOSHI Toshinori ID: 9000309984299

    Graduate School of Science and Technology, Kumamoto University (2014 from CiNii)

    Articles in CiNii:1

    • A hardware description method and semantics providing a timing constraint (2014)
  • SUEYOSHI Toshinori ID: 9000309985535

    Graduate School of Science and Technology, Kumamoto University (2014 from CiNii)

    Articles in CiNii:1

    • Looking Back over My Researches on Flexible Hardware : Reconfigurable Systems and FPGAs (2014)
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