Search Results1-20 of  26

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  • Keikichi" "Tamaru ID: 9000242466009

    Articles in CiNii:1

    • The Power Reduction Method of a Binary Number Comparator (2002)
  • Keikichi "Tamaru ID: 9000242465423

    Articles in CiNii:1

    • The Leakage Power Reduction of Execution Circuits by Power Switch Method (2005)
  • Keikichi "Tamaru ID: 9000242465879

    Articles in CiNii:1

    • The Approximate Delay Equations of DTMOS Circuits : In the Case of Slow Input (2003)
  • TAMARU Keikichi ID: 1000010127102

    Graduate School of Informatics, Kyoto University (1999 from CiNii)

    Articles in CiNii:117

    • Branch-and-Bound Placement for Building Block Layout (1992)
    • A Module Generator for the Improved Multiple Wave Fronts Configuration Multiplier (1995)
    • 16ビットマイクロプロセッサの動向 (マイクロコンピュ-タの技術環境特集号) (1984)
  • TAMARU Keikichi ID: 9000004375005

    Okayama University of Science (2004 from CiNii)

    Articles in CiNii:5

    • Flexible LSI Devices : FPGA (<Special Feature>Flexible Hardware) (1999)
    • C-12-1 Low Power Execution Circuits with Power Control Method (2004)
    • C-12-38 Memory Composition of Functional Memory Circuit for Block Matching (2004)
  • TAMARU Keikichi ID: 9000004789065

    Okayama University of Science (2000 from CiNii)

    Articles in CiNii:8

    • Model-Adaptable Parameter Extraction System for MOSFET Models (1995)
    • Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition (2000)
    • A Memory-Based Parallel Processor for Vector Quantization: FMPP-VQ (1997)
  • TAMARU Keikichi ID: 9000004792061

    the Department of Electronics and Communications, Kyoto University (1998 from CiNii)

    Articles in CiNii:1

    • Analytical Formulas of Output Waveform and Short-Circuit Power Dissipation for Static CMOS Gates Driving a CRC π Load (1998)
  • TAMARU Keikichi ID: 9000004793007

    Department of Communications and Computer Engineering, Kyoto University (1999 from CiNii)

    Articles in CiNii:1

    • A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits (1999)
  • TAMARU Keikichi ID: 9000004801619

    Department of Electronics, Kyoto University (1995 from CiNii)

    Articles in CiNii:1

    • Register-Transfer Module Selection for Sub-Micron ASIC Design (1995)
  • TAMARU Keikichi ID: 9000004802389

    Department of Electronics, Kyoto University (1996 from CiNii)

    Articles in CiNii:1

    • A Floorplan Based Methodology for Data-Path Synthesis of Sub-Micron ASICs (1996)
  • TAMARU Keikichi ID: 9000004804591

    Department of Electronics and Communication Engineering, Kyoto University (1998 from CiNii)

    Articles in CiNii:1

    • CAM-Based Array Converter for URR Floating-Point Arithmetic (1998)
  • TAMARU Keikichi ID: 9000004845620

    Faculty of Engineering, Kyoto University (1995 from CiNii)

    Articles in CiNii:1

    • Compaction with Shape Optimization and Its Application to Layout Recycling (1995)
  • TAMARU Keikichi ID: 9000004846627

    Faculty of Engineering, Kyoto University (1996 from CiNii)

    Articles in CiNii:1

    • Estimation of Short-Circuit Power Dissipation for Static CMOS Gates (1996)
  • TAMARU Keikichi ID: 9000004849191

    Department of Communications and Computer Engineering, Kyoto University (1999 from CiNii)

    Articles in CiNii:1

    • Layout Dependent Matching Analysis of CMOS Circuits (1999)
  • TAMARU Keikichi ID: 9000018306525

    Department of Electronic Engineering, Okayama University Graduate School (2006 from CiNii)

    Articles in CiNii:2

    • The Power Reduction of Execution Circuits with Dynamic Power Control Method (2004)
    • C-12-1 Leakage power reduction of CMOS logic circuits by power Switching (2006)
  • TAMARU Keikichi ID: 9000253319765

    東芝総合研究所電子機器研究所 (1972 from CiNii)

    Articles in CiNii:1

    • Application of Integrated Circuits in Measuring Equipments (1972)
  • Tamaru Keikichi ID: 9000004843790

    the Faculty of Engineering, Kyoto University (1993 from CiNii)

    Articles in CiNii:1

    • Design of a Multiplier-Accumulator for High Speed Image Filtering (1993)
  • Tamaru Keikichi ID: 9000004844420

    the Faculty of Engineering, Kyoto University (1993 from CiNii)

    Articles in CiNii:1

    • An Architecture for High Speed Array Multiplier (1993)
  • Tamaru Keikichi ID: 9000004844840

    Faculty of Engineering, Kyoto University (1994 from CiNii)

    Articles in CiNii:1

    • Experiments with Power Optimization in Gate Sizing (Special Section of Letters Selected from the 1994 IEICE Spring Conference) (1994)
  • Tamaru Keikichi ID: 9000004868756

    Faculty of Elctronics, Kyoto University (1993 from CiNii)

    Articles in CiNii:1

    • A Language for Designing Module Generators (Special Issue on Synthesis and Verification of Hardware Design) (1993)
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