Search Results1-20 of  34

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  • USAMI KIMIYOSHI ID: 9000241439632

    Articles in CiNii:1

    • Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units (LSI Design Methodology Vol.4) (2011)
  • Kimiyoshi Usami ID: 9000261053057

    Grad. of Science and Engineering, Waseda University | Dept. of Information Science and Engineering, Shibaura Insititute of Technology (2014 from CiNii)

    Articles in CiNii:1

    • Local pulse generation in variable stages pipeline designs for low energy consumption (2014)
  • USAMI KIMIYOSHI ID: 9000006816908

    Shibaura Institute of Technolog (2008 from CiNii)

    Articles in CiNii:1

    • Cache Controller Design With Run-time Power Gating (2008)
  • USAMI Kimiyoshi ID: 1000020365547

    Articles in CiNii:180

    • Low Power Technology in High-level Design (2005)
    • Power-Gating Circuit Scheme for Transient-Glitch Energy Reduction (2011)
    • Power-Gating Circuit Scheme for Transient-Glitch Energy Reduction (2011)
  • USAMI Kimiyoshi ID: 9000004826331

    Toshiba Corporation Semiconductor Company (2002 from CiNii)

    Articles in CiNii:1

    • Selective Multi-Threshold Technique for High-Performance and Low-Standby Applications (2002)
  • USAMI Kimiyoshi ID: 9000004828824

    Department of Information Science and Engineering, Shibaura Institute of Technology (2004 from CiNii)

    Articles in CiNii:1

    • Dynamic Sleep Control for Finite-State-Machines to Reduce Active Leakage Power (2004)
  • USAMI Kimiyoshi ID: 9000004970850

    Graduate School of Engineering, Shibaura Institute of Technology (2005 from CiNii)

    Articles in CiNii:2

    • Delay Modeling and Static Timing Analysis for MTCMOS Circuits (2005)
    • Delay Modeling and Static Timing Analysis for MTCMOS Circuits (2005)
  • USAMI Kimiyoshi ID: 9000016489031

    Graduate School of Engineering, Shibaura Institute of Technology (2006 from CiNii)

    Articles in CiNii:1

    • Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits (2006)
  • USAMI Kimiyoshi ID: 9000019134971

    Department of Information Science and Engineering, Shibaura Institute of Technology (2011 from CiNii)

    Articles in CiNii:1

    • Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model (2011)
  • USAMI Kimiyoshi ID: 9000107315178

    Shibaura Institute of Technology (2012 from CiNii)

    Articles in CiNii:1

    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • USAMI Kimiyoshi ID: 9000107318063

    Shibaura Institute of Technology (2012 from CiNii)

    Articles in CiNii:1

    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • USAMI Kimiyoshi ID: 9000107358407

    Shibaura Institute of Technology (2012 from CiNii)

    Articles in CiNii:1

    • Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router (2012)
  • USAMI Kimiyoshi ID: 9000107382192

    Articles in CiNii:1

    • A Fine Grain Dynamic Sleep Control Scheme in Superscalar Processor (2008)
  • USAMI Kimiyoshi ID: 9000242085198

    Department of Computer Science and Engineering, Waseda University|Department of Information Science and Engineering, Shibaura Institute of Technology|Department of Electronic and Photonic Systems, Waseda University (2013 from CiNii)

    Articles in CiNii:1

    • Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages (2013)
  • USAMI Kimiyoshi ID: 9000242085258

    Shibaura Institute of Technology (2013 from CiNii)

    Articles in CiNii:1

    • FOREWORD (2013)
  • USAMI Kimiyoshi ID: 9000261678786

    the Department of Information Science and Engineering, Shibaura Institute of Technology (2013 from CiNii)

    Articles in CiNii:1

    • Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design (2013)
  • USAMI Kimiyoshi ID: 9000283636436

    Shibaura Institute of Technology (2011 from CiNii)

    Articles in CiNii:1

    • Let’s go to IEICE Workshops!:VLSI Design Technologies (VLD) (2011)
  • USAMI Kimiyoshi ID: 9000297481742

    Department of Computer Science and Engineering, Waseda University|Department of Information Science and Engineering, Shibaura Institute of Technology|Department of Electronic and Photonic Systems, Waseda University (2015 from CiNii)

    Articles in CiNii:1

    • An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design (2015)
  • USAMI Kimiyoshi ID: 9000297482903

    Shibaura Institute of Technology (2015 from CiNii)

    Articles in CiNii:1

    • A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units (2015)
  • USAMI Kimiyoshi ID: 9000297482916

    Shibaura Inst. of Tech. (2015 from CiNii)

    Articles in CiNii:1

    • A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode (2015)
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