Search Results 1-20 of 368

  • Study on Parasitic Calibration Method of C-C SAR-ADC Using γ-Estimation  [in Japanese]

    関根 慧 , 松浦 達治 , 岸田 亮 , 兵庫 明

    電気学会研究会資料. ECT = The papers of technical meeting on electronic circuits, IEE Japan 2020(27-33・35-40), 43-47, 2020-03-09

  • Study on Radix-Estimation Algorithm of SAR-ADC Using C-C ladder  [in Japanese]

    関根 慧 , 松浦 達治 , 岸田 亮 , 兵庫 明

    電気学会研究会資料. ECT = The papers of technical meeting on electronic circuits, IEE Japan 2020(1-26), 51-56, 2020-01-23

  • A 16 bit 200 kS/s successive approximation register ADC with foreground on-chip self-calibration

    Zhang Zhenwei , Shan Yi , Dong Yemin

    … <p>In this paper, an 8-channel 16 bit 200 kS/s successive approximation register analog-to-digital converter (SAR ADC) realized in 130 nm SOI CMOS technology is presented. … A capacitor-resistor hybrid digital-to-analog converter (DAC) is adopted in this design to avoid the bulky capacitor array. …

    IEICE Electronics Express, 2020

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  • Effect of Hysteresis-based Simple Negative Feedback A/D Conversion on Channel Estimation for Single Carrier Modulation

    Kageyama Tomoya , Kanemoto Daisuke , Endo Oruto , Ohki Makoto , Muta Osamu

    … In particular, an analog-to-digital converter (ADC) is one of the most important circuit blocks. … To deal with this issue, a low-resolution ADC utilizing hysteresis-based simple negative feedback (SNF) technique (hysteresis-based SNF-ADC) was proposed to mitigate nonlinear distortion. …

    IEICE Communications Express, 2020

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  • A 16-bit 8-MS/s SAR ADC with a foreground calibration and hybrid-charge-supply power structure

    Zhang Zhenwei , Qiu Lei , Shan Yi , Dong Yemin

    … <p>In this paper, a 16-bit 8-MS/s successive approximation register analog-to-digital converter (SAR ADC) with a foreground calibration technique is proposed. … A nonbinary searching algorithm is adopted to speed up the conversion rate and overcome the incomplete settling of the reference voltage. …

    IEICE Electronics Express, 2020

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  • A Space-saving SAR-ADC using C-C ladder  [in Japanese]

    関根 慧 , 松浦 達治 , 岸田 亮 , 兵庫 明

    電気学会研究会資料. ECT = The papers of technical meeting on electronic circuits, IEE Japan 2019(80-100), 65-68, 2019-12-18

  • Effect, on Applying DWA to DC Measurement Purpose INS-SAR ADC  [in Japanese]

    工藤 龍平 , 松浦 達治 , 岸田 亮 , 兵庫 明

    電気学会研究会資料. ECT = The papers of technical meeting on electronic circuits, IEE Japan 2019(32-42), 47-50, 2019-06-20

  • A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting common-mode voltage and controlling input voltage range

    Son Jisu , Jang Young-Chan

    … <p>A capacitor digital-to-analog converter (CDAC), which boosts the common-mode voltage and controls the input voltage rang, is proposed to improve the dynamic range and linearity of a single-ended successive approximation register (SAR) analog-to-digital converter (ADC). …

    IEICE Electronics Express 16(22), 20190597-20190597, 2019

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  • An efficient background timing skew calibration technique for time-interleaving analog-to-digital converters

    Cao Yu , Miao Peng , Li Fei , Wang Huan

    … <p>An efficient background timing skew calibration algorithm is proposed in this article, which detects the sampling time mismatches in time-interleaving analog-to digital converter (TIADC) by estimating the skew-related errors with a reference channel and aligns the sampling edge of each sub-ADC to that of the reference channel by analog variable-delay lines in the negative feedback loop. …

    IEICE Electronics Express 16(15), 20190352-20190352, 2019

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  • Implementation of Smart Dressing Systems Based on Flexible pH Sensors Using PET Films

    YUN Seok-Oh , LEE Jung Hoon , LEE Jin , KIM Choul-Young

    … Because the electrodes are comprised of a working electrode and a reference electrode, the reference electrode was fabricated by synthesizing the Polyaniline (PANI) on Ag/AgCl, while the pH sensor has four channels to evenly measure the pH value in a wide area. …

    IEICE Transactions on Information and Systems E102.D(8), 1572-1575, 2019

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  • Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs

    LI Shaolan , SANYAL Arindam , LEE Kyoungtae , YOON Yeonam , TANG Xiyuan , ZHONG Yi , RAGAB Kareem , SUN Nan

    … <p>Ring voltage-controlled-oscillators (VCOs) are increasingly being used to design ΔΣ ADCs. … They have the merits of simple, highly digital and low-voltage tolerant, making them attractive alternatives for the classic scaling-unfriendly operational-amplifier-based methodology. … This paper aims to provide a summary on the advancement of VCO-based ΔΣ ADCs. …

    IEICE Transactions on Electronics E102.C(7), 509-519, 2019

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  • Non-Ideal Issues Analysis in a Fully Passive Noise Shaping SAR ADC

    CHEN Zhijie , WAN Peiyuan , LI Ning

    … <p>This paper discusses non-ideal issues in a fully passive noise shaping successive approximation register analog-to-digital converter. … The fully passive noise shaping techniques are realized by switches and capacitors without operational amplifiers to be scalable and power efficient. … order fully passive noise shaping SAR ADC with an 8-bit architecture and an OSR of 4.</p> …

    IEICE Transactions on Electronics E102.C(7), 538-546, 2019

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  • An LTPS Ambient Light Sensor System with Sensitivity Correction Methods in LCD

    NAKAMURA Takashi , TADA Masahiro , KIMURA Hiroyuki

    … It is designed as a 4-bit (16-step-grayscale) ALS and includes a noise subtraction circuit, a comparator as an analog-to-digital converter (ADC), 4-bit counters, and a parallel-to-serial converter. …

    IEICE Transactions on Electronics E102.C(7), 558-564, 2019

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  • Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector

    XU Zule , FIRDAUZI Anugerah , MIYAHARA Masaya , OKADA Kenichi , MATSUZAWA Akira

    … <p>This paper presents a type-I digital ring-based PLL with wide loop bandwidth to lower the ring oscillator's noise contribution. … The loop delay due to the D flip-flops at filter's output is compensated in order to lower the noise peak and stably achieve wide loop bandwidth. …

    IEICE Transactions on Electronics E102.C(7), 520-529, 2019

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  • A Low Voltage Stochastic Flash ADC without Comparator

    ZOU Xuncheng , NAKATAKE Shigetoshi

    … <p>A low voltage stochastic flash ADC (analog-to-digital converter) is presented, with an inverter-based comparative unit which is used to replace comparator for comparison. … The inverter-based comparative unit replacing a comparator enables us to decrease the number of transistors for area saving and power reduction. …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E102.A(7), 886-893, 2019

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  • A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS

    Chen Xubin , Li Xuan , Shen Yupeng , Liu Jiarui , Chen Hua

    … <p>In this paper, a 14 bit 500 MS/s SHA-less pipelined Analog-to-Digital Converter (ADC) realized in 40 nm CMOS technology is presented. … A 2.5 V powered buffer that exhibits a comprehensive bootstrap architecture is proposed to achieve the trade-off between linearity and power consumption. …

    IEICE Electronics Express 16(11), 20190197-20190197, 2019

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  • A 24-bit sigma-delta ADC with configurable chopping scheme

    Li Li , Cheng Xu , Zhang Zhang , Zeng Jianmin , Zeng Xiaoyang

    … <p>This paper presents a low-power high-precision sigma-delta analog-to-digital converter (ADC) mainly used for DC measurement, especially in applications with high input impedance. … A configurable chopping scheme is proposed to reduce the input-dependent residual offset caused by the clock feed-through. …

    IEICE Electronics Express 16(10), 20190176-20190176, 2019

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  • A 1 GS/s 12-bit pipelined folding ADC with a novel encoding algorithm

    Liu Huasen , Wu Danyu , Zhou Lei , Luan Jian , Guo Xuan , Wang Dong , Wu Jin , Liu Xinyu

    … <p>In this paper, a 1-GS/s 12-bit pipelined folding analog-to-digital converter (ADC) fabricated in 40 nm CMOS technology is presented. … A new encoding algorithm based on distributed quantization is proposed to simplify the quantization process of the structure with odd folding factor and reduce the hardware consumption of the circuit. …

    IEICE Electronics Express 16(7), 20181150-20181150, 2019

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  • A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

    Dai-guo Xu , Pu-Jie , Shi-liu Xu , Zheng-ping Zhang , Jun-an Zhang , Jian-an Wang

    … <p>A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique is proposed. … To demonstrate the proposed technique, a design of 12-bit 100-MS/s SAR ADC is fabricated in 40-nm CMOS technology, consuming 2 mW from 1 V power supply with a SNDR >65 dB and SFDR >83 dB. … The proposed ADC core occupies an active area of 0.02 mm<sup>2</sup>, and the corresponding FoM is 13.8 fJ/conversion-step with Nyquist frequency.</p> …

    IEICE Electronics Express 16(6), 20190007-20190007, 2019

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  • Delta-Sigma ADC Based on Switched-Capacitor Integrator with FIR Filter Structure

    SAIKATSU Satoshi , YASUDA Akira

    … The delta-sigma analog-to-digital converter (ΔΣADC) is used in various conversion systems to enable low-power, high-accuracy conversion using oversampling and noise shaping. … Increasing the gain coefficient of the integrator in the loop filter configuration of the ΔΣADC suppresses the quantization noise that occurs in the signal band. …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E102.A(3), 498-506, 2019

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