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  • Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation

    MAN Xin , HORIYAMA Takashi , KIMURA Shinji

    … Clock gating is supported by commercial tools as a power optimization feature based on the guard signal described in HDL (structural method). … Besides, since the clock gating cells also consume power, it is imperative to minimize the number of inserted clock gating cells and their switching activities for power optimization. …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 95(8), 1347-1358, 2012-08-01

    J-STAGE  References (11)

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