Search Results 1-20 of 203

  • A 0.4-V 6.6-<i>µ</i>W 75-dB SNDR delta-sigma modulator employing gate-body-driven amplifier with local CMFB loop and robust clock generator for implantable biomedical devices

    Chen Yan , Chen Yousheng , Guo Yan

    … <p>This paper presents an ultra-low-voltage (ULV) high-resolution low-power continuous-time delta-sigma modulator for implantable biomedical devices. … A robust clock generator is adopted to ensure modulator's consistent performances across ±10% power supply variation. …

    IEICE Electronics Express 17(11), 20200117-20200117, 2020

    J-STAGE 

  • A Wideband Real-Time Deception Jamming Method for Countering ISAR Based on Parallel Convolution

    TAI Ning , LIN Huan , WEI Chao , LU Yongwei , WANG Chao , CUI Kaibo

    … <p>Since ISAR is widely applied in many occasions and provides high resolution images of the target, ISAR countermeasures are attracting more and more attention. … The method processes the samples of radar signal in parallel and generates the jamming signal at the rate of ADC data, solving the problem that the real-time performance is not satisfied when the input data rate for convolution is far higher than the clock frequency of FPGA. …

    IEICE Transactions on Communications E103.B(5), 609-617, 2020

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  • An ultra-fast and high-precision VCO frequency calibration technique for fractional-N frequency synthesizers

    Liu Qi , Gan Yebing , Ye Tianchun

    … TOF affords the high-precision of the calibration and FSM with a high-speed clock offers the ultra-fast search. … The measured calibration time for a 5-bit capacitor bank is 90 ns for a frequency resolution of 203 KHz. …

    IEICE Electronics Express 17(7), 20200066-20200066, 2020

    J-STAGE 

  • Real Circuit Delay Measurement Method by Variable Frequency Operation with On-Chip Fine Resolution Oscillator

    Shimamura Kotaro , Ikeda Naohiro

    … In the proposed method, on-chip oscillator supplies fine resolution variable frequency clock to internal circuit. … Clock multiplication improves delay resolution, and repetitive measurement reduces measurement error caused by time dependent random delay variation. …

    IPSJ Transactions on System LSI Design Methodology 13(0), 21-30, 2020

    J-STAGE 

  • Analysis of TIADC channel mismatch effects on high-resolution range profile

    Li Jingyu , Xiao Dandan , Zhang Yue

    … <p>The wideband echo signals of the imaging radar can be processed by pulse compression to obtain high-resolution range profile (HRRP). … The resolution of HRRP is proportional to the signal bandwidth. … The pursuit of high resolution makes the bandwidth of radar transmitting signal larger and larger. …

    IEICE Electronics Express 17(1), 20190535-20190535, 2020

    J-STAGE 

  • On-chip test clock validation using a time-to-digital converter in FPGAs

    Miyake Yousuke , Kajihara Seiji , Chen Poki

    … While on-chip delay measurement combining logic BIST with a variable test clock is an effective way to secure field reliability of VLSI/FPGAs, validation of the variable test clock generated on the chip is important to guarantee measurement accuracy. … This paper addresses a method of on-chip test clock validation using a TDC (Time-to-Digital Converter) for FPGAs. …

    2019 IEEE International Test Conference in Asia (ITC-Asia), 2019-10-17

    IR 

  • Real Circuit Delay Measurement Method by Variable Frequency Operation with On-Chip Fine Resolution Oscillator  [in Japanese]

    島村 光太郎 , 池田 尚弘

    DAシンポジウム2019論文集 (2019), 3-8, 2019-08-21

    IPSJ 

  • Current-feedback-stabilized laser system for quantum simulation experiments using Yb clock transition at 578 nm

    Takata Y. , Nakajima S. , Kobayashi J. , Ono K. , Amano Y. , Takahashi Y.

    … We developed a laser system for the spectroscopy of the clock transition in ytterbium (Yb) atoms at 578 nm based on an interference-filter stabilized external-cavity diode laser (IFDL) emitting at 1156 nm. … Using this laser system, we performed high-resolution clock spectroscopy of Yb and found that the linewidth of the stabilized laser was less than 320 Hz. …

    Review of Scientific Instruments 90(8), 2019-08

    IR 

  • FUTURE PROJECTION OF SPECTRAL WAVE CLIMATE AROUND JAPAN  [in Japanese]

    SHIMURA Tomoya , MORI Nobuhito

    <p> 将来気候変動条件下における日本沿岸の高解像度波候予測を実施した.将来気候における有義波高と平均周期の気候値は,現在気候と比較してそれぞれ10%および3%程度の減少を示した.有義波高と平均周期の統計量に加えて,期間平均方向スペクトルの将来変化を解析した.日本沿岸で,平均方向スペクトルの全帯域でエネルギーが減少することにより,有義波高および平均周期の減少につながる.平均波向きは,日 …

    Journal of Japan Society of Civil Engineers, Ser. B2 (Coastal Engineering) 75(2), I_1177-I_1182, 2019

    J-STAGE 

  • Lightwave-driven Dirac currents in a topological surface band  [in Japanese]

    KIMURA Akio

    <p>もし,振動電場としての光の1周期よりも短い時間でスピン偏極電子を制御できれば,光の周波数で駆動する超高速スピントロニクスの実現が可能になるだろう.このような光の1周期より短い分解能を備えた時間・角度分解光電子分光(ARPES)を行うことにより,トポロジカル絶縁体表面のディラック電子がテラヘルツ光電場によりバンド内で加速され,最大2A/cmもの大きな電流密度が発生することがわかった …

    Oyo Buturi 88(7), 445-451, 2019

    J-STAGE 

  • An ultra-low power robust CMOS temperature sensor with an inaccuracy of ±0.7°C from −40°C to 85°C

    Hu Yi , Hou Jiali , Zhang Jianyun , Zhang David Wei , He Yang

    … A smart clock generator is also proposed to adapt the change of PTAT bias current, which provides the integrators more settling time in low temperature with low bias current and makes the delta-sigma ADC faster in high temperature to reduce the error caused by leakage. … After a one-point temperature trimming, the sensor has a resolution of 0.015 from −40°C to 85°C, and only consumes 10 µA from 1.5 V supply.</p> …

    IEICE Electronics Express 16(16), 20190381-20190381, 2019

    J-STAGE 

  • A 0.3-to-5.5 GHz Digital Frequency Discriminator IC with Time to Digital Converter and Edge Counter for Instantaneous Frequency Measurement

    HIRAI Akihito , TSUTSUMI Koji , NAKAMIZO Hideyuki , TANIGUCHI Eiji , TAJIMA Kenichi , MORI Kazutomi , TSURU Masaomi , SHIMOZAWA Mitsuhiro

    … <p>In this paper, a high-frequency resolution Digital Frequency Discriminator (DFD) IC using a Time to Digital Converter (TDC) and an edge counter for Instantaneous Frequency Measurement (IFM) is proposed. … By measuring the multiple periods with the TDC and the edge counter, the proposed DFD improves the frequency resolution compared with that of the measuring one period because it is proportional to reciprocal of the measurement time of TDC. …

    IEICE Transactions on Electronics E102.C(7), 547-557, 2019

    J-STAGE 

  • Dynamic Performance Adjustment of CPU and GPU in a Gaming Notebook at the Battery Mode

    CHENG Chun-Hung , BAI Ying-Wen

    … In order to extend the operation time at the battery mode, in general, the notebook computer will directly reduce the clock rate and then reduce the performance. … This design can obtain the necessary balance of the performance and the power consumption by using both the EC and the BIOS cooperatively to implement the dynamic control of both the CPU and the GPU frequency to maintain the system performance at a sufficient level for a high speed and high resolution video game. …

    IEICE Transactions on Information and Systems E102.D(7), 1257-1270, 2019

    J-STAGE 

  • URBAN CLIMATIC ZONING USING MSSG MODEL AND MULTIVARIABLE ANALYSIS:For making urban environmental climate maps of Yokohama considering microtopography  [in Japanese]

    YOKOYAMA Makoto , TANAKA Takahiro , SUGIYAMA Toru , SADOHARA Satoru

    … However, spatial resolution of such numerical calculation is relatively rough, and the influence of microtopography can't be reflected. …

    Journal of Environmental Engineering (Transactions of AIJ) 84(759), 533-542, 2019

    J-STAGE 

  • A 24-bit sigma-delta ADC with configurable chopping scheme

    Li Li , Cheng Xu , Zhang Zhang , Zeng Jianmin , Zeng Xiaoyang

    … A configurable chopping scheme is proposed to reduce the input-dependent residual offset caused by the clock feed-through. … Measurement results show that the ADC achieves 20-bit resolution, 10 ppm INL and a 0.6 µV offset, while consuming 860 µW from 3.3 V supply.</p> …

    IEICE Electronics Express 16(10), 20190176-20190176, 2019

    J-STAGE 

  • A Case of Diffuse Esophageal Spasm Treated with Peroral Endoscopic Myotomy

    Sugihara Yuusaku , Harada Keita , Kato Ryo , Yamauchi Kenji , Sakae Hiroyuki , Kawano Seiji , Hiraoka Sakiko , Kawahara Yoshiro , Otsuka Fumio , Okada Hiroyuki

    … Endoscopy and upper gastrography revealed abnormal peristaltic movements involving interruption of normal peristalsis, and a diverticulum located at the 2 o'clock esophageal position. … High-resolution manometry indicated DES. …

    Acta Medica Okayama 72(6), 595-600, 2018-12

    IR  DOI  Ichushi Web 

  • Software-type Wave–Particle Interaction Analyzer on board the Arase satellite

    Katoh Yuto , Kojima Hirotsugu , Hikishima Mitsuru , Takashima Takeshi , Asamura Kazushi , Miyoshi Yoshizumi , Kasahara Yoshiya , Kasahara Satoshi , Mitani Takefumi , Higashio Nana , Matsuoka Ayako , Ozaki Mitsunori , Yagitani Satoshi , Yokota Shoichiro , Matsuda Shoya , Kitahara Masahiro , Shinohara Iku

    … In the Arase satellite, a dedicated system has been developed to realize the time resolution required for inter-instrument communication. … Here, both the time index distributed over all instruments through the satellite system and an S-WPIA clock signal are used, that are distributed from the PWE to the MEP-e, HEP, and XEP through a direct line, for the synchronization of instruments within a relative time accuracy of a few μs. …

    Earth, Planets and Space (70), 2018-01-08

    IR 

  • Applicability of flood forecasting for the next 72 hours in the northern Kyushu on July 2017  [in Japanese]

    Nakamura Yosuke , Ushiyama Tomoki , Abe Shiori

    本研究は,出水が起こる可能性を数日前に検知できていたのかを明らかにすることを目的として,領域気象モデルWRFとRRIモデルを用いて検証した.<br>予測雨量はWRF-LETKFを用い,6時間毎に72時間先までを33個のアンサンブルメンバーで計算する.対象流域において見逃すことのないように空間分布の45kmを上限として平面的に雨域を移動させた.水文モデルはRRIモデルを用い,空間解像度が …

    Proceeding of Annual Conference 31(0), 34, 2018

    J-STAGE 

  • An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines

    SHIBATA Nobutaro , NAKAMURA Mitsuo

    … <p>Timing vernier (i.e., digital-to-time converter) is a key component of the pin-electronics circuit board installed in automated digital-VLSI test equipment, and it is used to create fine delays of less than one-cycle time of a clock signal. … Every macro installed in a real-time timing-signal generator VLSI achieved the required timing resolution of 31.25ps with a linearity error within 15ps. The on-the-fly jitter was successfully suppressed to a random jitter level (<26ps p-p).</p> …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E101.A(8), 1185-1196, 2018

    J-STAGE 

  • A low power and glitch-free circular rotation phase modulator for outphasing transmitter

    Wang Yang , Xie Lin-lin , Hei Yong , Qiao Shu-shan

    … The proposed modulator uses a path-shared tapped delay line (TDL) and a dynamical pseudo clock-gating control technique. … In addition, this chip achieves an 80 ps coarse resolution with 4.7 ps RMS error and a minimum phase resolution of 0.96 ps.</p> …

    IEICE Electronics Express 15(14), 20180406-20180406, 2018

    J-STAGE 

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