Search Results 1-20 of 203

  • Reducing CPU Power Consumption with Device Utilization-Aware DVFS for Low-Latency SSDs

    IMAMURA Satoshi , YOSHIDA Eiji , OE Kazuichi

    … Since the OS processing is executed on a CPU core, its operating frequency should be maximized for reducing the OS overhead. … However, a higher core frequency causes the higher CPU power consumption during I/O accesses to low-latency SSDs. …

    IEICE Transactions on Information and Systems E102.D(9), 1740-1749, 2019

    J-STAGE 

  • Transient Response of a Digitally Controlled Power Supply Based on Power-SoC

    Oka Toshiomi , Abe Seiya , Matsumoto Satoshi

    … POLs (Point of Load) have become important technology because they can suppress the voltage drop and reduce the power consumption of MCUs (Micro controller Unit). … The key applications of power SoC are DVFS(Dynamic Voltage and Frequency Scaling) and envelope tracking. … These applications are required fast transient response for output voltage. …

    Proceedings of Integrated Power Conversion and Power Management (PwrSoc 2018), 2018-10

    IR 

  • Cache Energy Reduction by Dynamically Switching The Highest-level Caches during Surplus Time Due to DVFS  [in Japanese]

    齋藤 郁 , 小林 良太郎 , 嶋田 創

    IoTデバイスやスマートデバイスに搭載されるSystem-on-a-Chip(SoC)アーキテクチャの中で,CPUに着目すると,内包されているキャッシュメモリの消費電力割合が大きい.回路の省電力化には,最低限の電圧を供給するような電源管理がよく用いられるが,キャッシュはプロセスルールの微細化の影響で供給電圧を大幅に下げることが困難であり,電源管理による省電力化の効果が小さい.そこで本論文では,キャ …

    情報処理学会論文誌 59(3), 1061-1076, 2018-03-15

    IPSJ 

  • Reducing Jitter and Energy in Hard Real-time Systems Using Intra-task DVFS Technique

    Boyu Tseng , 田中 清史

    Dynamic Voltage and Frequency Scaling (DVFS) technique enables systems to proactively manipulate actual execution/response time of tasks. … The strategy proposed in this study mainly applies control and data flow analysis to insert additional frequency scaling code (instructions to change processor's voltage and frequency). …

    第80回全国大会講演論文集 2018(1), 113-114, 2018-03-13

    IPSJ 

  • Quantized Decoder Adaptively Predicting both Optimum Clock Frequency and Optimum Supply Voltage for a Dynamic Voltage and Frequency Scaling Controlled Multimedia Processor

    KOBAYASHI Nobuaki , ENOMOTO Tadayoshi

    … <p>To completely utilize the advantages of dynamic voltage and frequency scaling (DVFS) techniques, a quantized decoder (QNT-D) was developed. … is used to produce the optimum frequency (opt.<i>f</i><sub>c</sub>) and the optimum supply voltage (opt.<i>V</i><sub>D</sub>) that are proportional to <i>Q</i>. …

    IEICE Transactions on Electronics E101.C(8), 671-679, 2018

    J-STAGE 

  • Energy Efficient Mobile Positioning System Using Adaptive Particle Filter

    KIM Yoojin , SONG Yongwoon , LEE Hyukjun

    <p>An accurate but energy-efficient estimation of a position is important as the number of mobile computing systems grow rapidly. A challenge is to develop a highly accurate but energy efficient …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E101.A(6), 997-999, 2018

    J-STAGE 

  • A low power QRS detection processor with adaptive scaling of processing resolution

    Chen Zhijian , Jia Menghan , Luo Jiahui , Zhu Taotao , Xiang Xiaoyan , Meng Jianyi

    … As reducing the resolution of electrocardiogram (ECG) data in certain degree has little effect on the detection accuracy but helps cut down the calculation power, a total of eight processing resolutions are supported in the processor, which can bring different levels of dynamic power reduction. …

    IEICE Electronics Express 15(1), 20170882-20170882, 2018

    J-STAGE 

  • A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing

    HOKIMOTO Shu , ISHIHARA Tohru , ONODERA Hidetoshi

    … <p>Scaling the supply voltage (<i>V</i><sub>dd</sub>) and threshold voltage (<i>V</i><sub>th</sub>) for minimizing the energy consumption of processors dynamically is highly desired for applications such as wireless sensor network and Internet of Things (IoT). …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100.A(12), 2776-2784, 2017

    J-STAGE 

  • A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation

    SHIOMI Jun , ISHIHARA Tohru , ONODERA Hidetoshi

    … <p>Scaling supply voltage (<i>V</i><sub>DD</sub>) and threshold voltage (<i>V</i><sub>th</sub>) dynamically has a strong impact on energy efficiency of CMOS LSI circuits. … simultaneously under dynamic workloads are thus widely investigated over the past 15 years. …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100.A(12), 2764-2775, 2017

    J-STAGE 

  • A 1.3 V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system

    Min Young-Jae , Jeong Chan-Hui , Moon Junil , Han Youngsun , Kim Soo-Won , Kim Chulwoo

    … The measured recovery time is less than 0.32 us when the load step-up time is 0.1 us from 2.5 mA to 120 mA, and the step-down time is 0.1 us at 1.2 V of supply voltage. … Moreover, the voltage spikes are less than 190 mV.</p> …

    IEICE Electronics Express 14(13), 20170461-20170461, 2017

    J-STAGE 

  • A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs

    Kong Joonho , Lee Kwangho

    … <p>Multiple clock domains mobile SoCs typically adopt dynamic voltage and frequency scaling (DVFS) for flexible power/energy management. …

    IEICE Electronics Express 14(11), 20170324-20170324, 2017

    J-STAGE 

  • Applying Razor Flip-Flops to SRAM Read Circuits

    JIMBO Ushio , YAMADA Junji , SHIOYA Ryota , GOSHIMA Masahiro

    … <p>Timing fault detection techniques address the problems caused by increased variations on a chip, especially with dynamic voltage and frequency scaling (DVFS). … however, the naive application of Razor FFs to dynamic precharged logic such as SRAM read circuits is not effective. …

    IEICE Transactions on Electronics E100.C(3), 245-258, 2017

    J-STAGE 

  • Response Time Constrained CPU Frequency and Priority Control Scheme for Improved Power Efficiency in Smartphones

    JO Sung-Woong , HA Taeyoung , KYONG Taehyun , CHUNG Jong-Moon

    … <p>Dynamic voltage and frequency scaling (DVFS) is an essential mechanism for power saving in smartphones and mobile devices. … In this paper, the response time is mathematically modeled by considering the CPU frequency and characteristics of the running applications based on the Linux kernel's completely fair scheduler (CFS), and a Response time constrained Frequency & …

    IEICE Transactions on Information and Systems E100.D(1), 65-78, 2017

    J-STAGE 

  • Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems

    BEN AHMED Akram , MATSUTANI Hiroki , KOIBUCHI Michihiro , USAMI Kimiyoshi , AMANO Hideharu

    … <p>In this paper, the Multi-voltage (multi-Vdd) variable pipeline router is proposed to reduce the power consumption of Network-on-Chips (NoCs) designed for Chip Multi-processors (CMPs). … The multi-Vdd variable pipeline router adjusts its pipeline depth (i.e., communication latency) and supply voltage level in response to the applied workload. …

    IEICE Transactions on Electronics E99.C(8), 909-917, 2016

    J-STAGE 

  • A Slack Reclamation Method for Reducing the Speed Fluctuations on the DVFS Real-Time Scheduling

    CHEN Da-Ren , HSU Chiun-Chieh , CHEN Hon-Chan

    … <p>Dynamic Voltage/Frequency Scaling (DVFS) allows designers to improve energy efficiency through adjusting supply voltage at runtime in order to meet the workload demand. … Other solutions for online scheduling depend on empirical or stochastic heuristics, which potentially result in frequent fluctuations of voltage/speed scaling. …

    IEICE Transactions on Electronics E99.C(8), 918-925, 2016

    J-STAGE 

  • Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control

    ANDO Hideki , SHIOYA Ryota

    Dynamic instruction window resizing (DIWR) is a scheme that effectively exploits both memory-level parallelism and instruction-level parallelism by configuring the instruction window size appropriately for exploiting each parallelism. …

    IEICE Transactions on Information and Systems E99.D(2), 341-350, 2016

    J-STAGE 

  • Energy-aware Task Scheduling for a Manycore Processor with Coarse Grain Voltage Domains  [in Japanese]

    和田 康孝 , 近藤 正章 , 本多 弘樹

    … 消費電力・消費エネルギーの低減は今日のあらゆるコンピュータシステムにおいて最も重要な課題の1つである.電力効率の向上のため,DVFS(Dynamic Voltage/Frequency Scaling)やPG(Power Gating)が広く用いられているが,並列アプリケーションに対してこれらの技術を適切に適用するのは難しい.加えて,メニーコア化により1チップ上に集積されるコア数の増加は著 …

    情報処理学会論文誌コンピューティングシステム(ACS) 8(1), 34-50, 2015-03-26

    IPSJ 

  • A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications

    CHANG Chia-Wen , CHU Yuan-Hua , JOU Shyh-Jye

    … This paper presents a cell-based all-digital phase-locked loop (ADPLL) with hierarchical gated digitally controlled oscillator (G-DCO) for low voltage operation, wide frequency range as well as low-power consumption. … In addition, a new time-domain hierarchical frequency estimation algorithm (HFEA) for frequency acquisition is proposed to estimate the output frequency in 1.5M<sub>F</sub> …

    IEICE Transactions on Electronics E98.C(8), 882-891, 2015

    J-STAGE 

  • A wide-range and fast-locking all digital SARDLL for DVFS SoCs

    Xu Tai-Long , Xue Feng , Cai Zhi-Kuang , Gao Xian-He , Hu Xue-You , Zha Chang-Jun , Xu Yu-Feng , Chen Jun-Ning

    … A wide-range and fast-locking all digital successive approximation register-controlled delay-locked loop (SARDLL) is presented for dynamic voltage/frequency scaling (DVFS) system-on-chips (SoCs). … The power consumption is estimated to be 0.72 mW at 1.2 V supply voltage and 2-GHz clock frequency. …

    IEICE Electronics Express 12(12), 20150284-20150284, 2015

    J-STAGE 

  • A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage

    KAMAE Norihiro , TSUCHIYA Akira , ONODERA Hidetoshi

    … Demonstration of the AES core shows a successful operation with the supply voltage from 0.5 V to 1.2 V which enables the reduction of power dissipation, for example, of 17% at 400 MHz operation. …

    IEICE Transactions on Electronics E98.C(6), 504-511, 2015

    IR  J-STAGE 

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