Search Results 1-20 of 202

  • A Study on Effect of Speed Adjustment Delineator on Driver's Risk Avoiding Behavior with the Merging Vehicle in the case of using Adaptive Cruise Control System  [in Japanese]

    KAWAI Rena , HAGIWARA Toru , TAKAHASHI Sho , TERAKURA Yoshihiro , OISHI Yusuke

    <p>本研究では,高速道路本線で ACC を用いた運転を行っているドライバの合流車との錯綜を軽減するために,事前の速度調整装置として走行車線中央に埋め込んだ速度誘導灯を提案した.ドライビングシミュレータを用いて 46 名の実験参加者で走行実験を行い,走行記録・主観評価などから速度誘導灯の意図に関する説明の違いがドライバの運転行動に影響を与えることが示された.その中で,速度誘導灯の意図を …

    JSTE Journal of Traffic Engineering 7(2), A_316-A_325, 2021

    J-STAGE 

  • The Teaching Method for Self-Regulated Learning by Wigfield:An Fused Approach of  Inquiry Science Activities and Reading Strategy Instruction in CORI  [in Japanese]

    HOSOYA Tomohiro

    <p>自己調整学習とCORI の関係性については,CORI 開発者の一人であるウィグフィールドによって,いくつかの著書で自己調整学習の一例として紹介されている。しかし,そこでは自己調整学習のための指導をどのようにCORI で具体化させたのかという点が,詳細に明示されているわけではない。この関係性を特徴づけることは,自己調整学習のための指導方法を日本で実践する上でも示唆に富むと思われる。 …

    Research Journal of Educational Methods 45(0), 25-35, 2020

    J-STAGE 

  • RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining

    MIYAZAKI Hiromu , KANAMORI Takuto , ISLAM Md Ashraful , KISE Kenji

    … The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. … We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. …

    IEICE Transactions on Information and Systems E103.D(12), 2494-2503, 2020

    J-STAGE 

  • Efficient method to evaluate misalignment between virtual and real objects for AR-based assembly assistance system

    Li Ting-Hao , Suzuki Hiromasa , Ohtake Yutaka , Yatagawa Tatsuya , Matsuda Shinji

    … <p>For complex assembly, it is important to give a user concise and effective assembly instructions for efficient assembly operation and training. … It is evaluated by computing the distance between the virtual object (CAD model) and the digital information of the real object that is the points scanned by a depth camera embedded in HoloLens. …

    Proceedings of JSPE Semestrial Meeting 2020S(0), 224-225, 2020

    J-STAGE 

  • Design and Implementation of Superinstructions for JavaScript Virtual Machine Generation System for Embedded Systems eJSTK

    Tomoya Nonaka , Tomoharu Ugawa

    Embedded systems generally have a small amount of memory and slow CPUs. … In this research, we introduce superinstructions, combinations of constant load instructions and arithmetic, logical, and relational (ALR) instructions to increase execution speed. … Thus, we designed superinstructions so that they would share their implementation code with the ALR instructions, from which they are made. …

    情報処理学会論文誌プログラミング(PRO) 12(3), 2019-09-18

    IPSJ 

  • An Implementation of 3D Registration of Objects for AR Application Using HMD  [in Japanese]

    LI Ting-Hao , SUZUKI Hiromasa , OHTAKE Yutaka , YATAGAWA Tatsuya , MATSUDA Shinji

    … In this research, a scheme is proposed to evaluate the transformation relationship only using HMD of Microsoft HoloLens for mixed reality with an embedded depth camera. … With this preliminary development, this scheme would be potential for not only assembly instruction but also assembly inspection to give instructions for the correction when the misassembly occurs.</p> …

    The Proceedings of Design & Systems Conference 2019.29(0), 2302, 2019

    J-STAGE 

  • Design and Implementation of Superinstructions for JavaScript Virtual Machine Generation System for Embedded Systems eJSTK

    Nonaka Tomoya , Ugawa Tomoharu

    … <p>Embedded systems generally have a small amount of memory and slow CPUs. … In this research, we introduce superinstructions, combinations of constant load instructions and arithmetic, logical, and relational (ALR) instructions to increase execution speed. … Thus, we designed superinstructions so that they would share their implementation code with the ALR instructions, from which they are made. …

    Journal of Information Processing 27(0), 658-670, 2019

    J-STAGE 

  • Evaluation of Register Number Abstraction for Enhanced Instruction Register Files

    FUJIEDA Naoki , SATO Kiyohiro , IWAMOTO Ryodai , ICHIKAWA Shuichi

    … <p>Instruction set randomization (ISR) is a cost-effective obfuscation technique that modifies or enhances the relationship between instructions and machine languages. … An Instruction Register File (IRF), a list of frequently used instructions, can be used for ISR by providing the way of indirect access to them. …

    IEICE Transactions on Information and Systems E101.D(6), 1521-1531, 2018

    J-STAGE 

  • IXM: Rapid Inter-process Communication Middleware for Robotics Software  [in Japanese]

    菅谷 みどり , 松原 豊 , 住谷 拓馬 , 中野 美由紀

    近年,接客ロボット,救助支援ロボットやドローンなど,自律的に行動する自律型ロボットの高機能化,複雑化が著しい.我々は,高齢者の行動を追従して,転倒を検出する高齢者見守りロボットを開発している.ロボット制御ソフトウェアの開発においては,機能ごとに別々のプログラムを開発し,それらのプログラム間でセンサ値や制御命令などのデータを通信することで,互いに連携できるよう支援するミドルウェアが用いられる.ROS …

    情報処理学会論文誌 58(10), 1578-1590, 2017-10-15

    IPSJ 

  • Development of a Programming Teaching-Aid Robot with Intuitive Motion Instruction Set

    Noguchi Takafumi , Kajiwara Hidekazu , Chida Kazunori , Inamori Sakae

    … <p>A robot that consists of a compact disc (CD) and an embedded microcomputer has been developed as a robotics learning tool for elementary and junior high school students. … In addition, intuitive instructions can be used to control the robot. … The program instructions can be viewed on the robot's 8 LEDs-display interface. …

    Journal of Robotics and Mechatronics 29(6), 980-991, 2017

    J-STAGE 

  • Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm

    XIAO Shanlin , ISSHIKI Tsuyoshi , LI Dongju , KUNIEDA Hiroaki

    … Standard off-the-shelf embedded processors are hard to meet the trade-offs among performance, power consumption and flexibility required by object detection applications. … With adding pipeline stages, application-specific hardware components and custom instructions, the AdaBoost algorithm is accelerated by a factor of 13.7x compared to the optimized pure software implementation. …

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100.A(7), 1384-1395, 2017

    J-STAGE 

  • Medicine instruction support system by sensor embedded intelligent cup  [in Japanese]

    OSADA Takuya , SUZUKI Takuo , NAKAUCHI Yasushi

    … In this paper, we propose a sensor-embedded intelligent cup that provides instructions for correct dosing and a medicine instruction support system using it. …

    Transactions of the JSME (in Japanese) 83(853), 17-00118-17-00118, 2017

    J-STAGE 

  • Fast Montgomery Modular Multiplication and Squaring on Embedded Processors

    LI Yang , WANG Jinlin , ZENG Xuewen , YE Xiaozhou

    … On resource-constraint embedded processors, memory-access operations play an important role as arithmetic operations in the modular multiplication. … To improve the efficiency of Montgomery modular multiplication on embedded processors, this paper concentrates on reducing the memory-access operations through adding a few working registers. … Then, we implement the algorithms on general MIPS64 processor and OCTEON CN6645 processor equipped with specific multiply-add instructions. …

    IEICE Transactions on Communications E100.B(5), 680-690, 2017

    J-STAGE 

  • Design and Implementation of Generation Framework for Instruction Set Simulators  [in Japanese]

    奥田 勝己 , 竹山 治彦

    命令セットシミュレータ(ISS:Instruction Set Simulator)は,組込みシステムの開発に不可欠なソフトウェアである.組込みシステムの開発では,新規アーキテクチャのプロセッサや専用プロセッサを含む多種多様なプロセッサが採用される.このため,組込みシステムの開発にISSを適用するためには,ISSの効率的な開発手法が必要である.そこで,本論文では,ISSの開発効率化を目的としたIS …

    情報処理学会論文誌 57(8), 1718-1736, 2016-08-15

    IPSJ 

  • Classification of an Embedded System Instruction EMI Using a Deep Convolutional Neural Network

    Shih-Yi Yuan , Po-Yen Lin , Cheng-You Chang , Jian-Li Dong , Chia-Hung Su

    IEICE Proceeding Series (58), WedAM2B.1, 2016

    DOI 

  • Area-efficient IoT MCU with remote code execution layer for cloud-connected code executable things

    Park Daejin

    … In this paper, a newly designed on-demand remote code execution layer of the microcontroller bus architecture is proposed that enables seamless execution of the accessed instructions, which are dynamically loaded from the cloud side in the runtime. …

    IEICE Electronics Express 13(12), 20160449-20160449, 2016

    J-STAGE 

  • Adhesion of different resin cements to enamel and dentin

    NAUMOVA Ella A. , ERNST Saskia , SCHAPER Katharina , ARNOLD Wolfgang H. , PIWOWARCZYK Andree

    … Teeth were embedded, ground flat to expose enamel or dentin and polished with sandpaper. … Adhesive systems were applied according to the manufacturers'instructions. …

    Dental Materials Journal 35(3), 345-352, 2016

    J-STAGE 

  • Dalvik Bytecode Acceleration Using Fetch/Decode Hardware Extension

    Thongkaew Surachai , Isshiki Tsuyoshi , Li Dongju , Kunieda Hiroaki

    … The experimental results show the speed improvements on Arithmetic instructions, loop & conditional instructions and method invocation & return instructions, can be achieved up to 2.4x, 2.7x and 1.8x, respectively. …

    Journal of information processing 23(2), 118-130, 2015-03-15

    IPSJ  J-STAGE 

  • Real-time Static Voltage and Frequency Scaling on RMT Processor with Instructions Per Clock Cycle Control  [in Japanese]

    YAMADA Kenji , HATORI Yusuke , HAGIWARA Shuma , MIZOTANI Keigo , TAKASU Masayoshi , YAMASAKI Nobuyuki

    … ProcessorはSimultaneous Multithreadedプロセッサであるためスループットが高く,スレッドの資源利用に対する優先度設定やInstructions Per Clock cycle (IPC)制御機構といったリアルタイム処理をサポートする機能を持つ.また,System in Packageに集積されたデバイスによりReal-Time Static Voltage and Frequency Scaling(RT-SVFS)を実現しており,消費電力削減の要求を満たすことができる.しかしRMT Processorでは負荷が偏ると高負荷の論理プロセッサがボト …

    IEICE technical report. Computer systems 114(506), 101-106, 2015-03-06

  • A Resource Utilization Aware Method to Improve Throughput on RMT Processor  [in Japanese]

    MURATA Taro , KANEDA Kensuke , TAKASU Masayoshi , MIZOTANI Keigo , HATORI Yusuke , YAMASAKI Nobuyuki

    … 行時間の予測性の低下はリアルタイム性が求められる組込み向けプロセッサにおいて問題となる.そのためRMTP(Responsive MultiThreaded Processor)は実行時間の予測性を高めるためにスレッドの実行速度を制御するIPC(Instructions Per Clock cycle)制御機構をもつ.しかし,IPC制御はスレッドのスループットを低下させる.そこで本研究では, RMTPにおいて,特にリアルタイム性が要求されるスレッドにのみIPC制御を適用し,その他のスレッドのス …

    IEICE technical report. Computer systems 114(506), 25-30, 2015-03-06

Page Top