Search Results 1-14 of 14

  • 1P1-C01 A Development of Small-sized Realtime Controller with MCU and FPGA  [in Japanese]

    TOMOKUNI Nobuyasu

    … In this paper, A small-sized real-time controller circuit board with MCU (Micro Control Unit) and FPGA (Field Programmable Gate Array) is described. … A MCU of this controller supports real time OS, network interface and floating point unit. …

    The Proceedings of JSME annual Conference on Robotics and Mechatronics (Robomec) 2015(0), _1P1-C01_1-_1P1-C01_2, 2015

    J-STAGE 

  • Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm<sup>2</sup> Nb Process

    PENG Xizhu , YAMANASHI Yuki , YOSHIKAWA Nobuyuki , FUJIMAKI Akira , TAKAGI Naofumi , TAKAGI Kazuyoshi , HIDAKA Mutsuo

    … In this architecture, a large number of SFQ floating-point units (FPUs) are used as core components, and their high performance and low power consumption are essential. … In this research, we implemented an SFQ half-precision bit-serial floating-point multiplier (FPM) with a target clock frequency of 50GHz, using the AIST 10kA/cm<sup>2</sup> … The FPM was designed, based on a systolic-array architecture. …

    IEICE Transactions on Electronics E97.C(3), 188-193, 2014

    J-STAGE 

  • Comparison of Fixed Point and Floating Point Calculations for Parallel Processing of FDTD Method Using FPGA  [in Japanese]

    TAKASU Ryota , HASEGAWA Tempei , TOMIOKA Yoichi , SHIBATA Tsugimichi , NAKANISHI Mamoru , KITAZAWA Hitoshi

    … In this paper, we discuss the advantages and disadvantages of fixed point and floating point arithmetic calculations of different bit lengths for parallel processing of FDTD method using FPGA. … A processing element (PE) for a fixed point arithmetic calculation is comparable small, and it is suitable to implement more PEs while the precision is restricted. …

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 113(26), 45-50, 2013-05-10

  • Evaluation Environment for Configuration of Floating-Point Unit Arrays  [in Japanese]

    ITOH Yuya , TAKASE Hideki , TAKAGI Kazuyoshi , TAKAGI Naofumi

    … A floating-point unit array that is constructed by connecting floating-point units, is expected to be an excellent architecture for calculating a huge amount of operation in scientific computation such as signal and image processing. …

    IEICE technical report. Computer systems 112(481), 253-258, 2013-03-13

  • Evaluation Environment for Configuration of Floating-Point Unit Arrays  [in Japanese]

    ITOH Yuya , TAKASE Hideki , TAKAGI Kazuyoshi , TAKAGI Naofumi

    … A floating-point unit array that is constructed by connecting floating-point units, is expected to be an excellent architecture for calculating a huge amount of operation in scientific computation such as signal and image processing. …

    IEICE technical report. Dependable computing 112(482), 253-258, 2013-03-13

  • Evaluation Environment for Configuration of Floating-Point Unit Arrays  [in Japanese]

    伊藤 勇也 , 高瀬 英希 , 高木 一義 , 高木 直史

    … レイの構成を検討することができる.本稿では,評価環境の適用例を挙げ,アレイの構成やデータ表現の検討における評価環境の有用性を示す.A floating-point unit array that is constructed by connecting floating-point units, is expected to be an excellent architecture for calculating a huge amount of operation in scientific computation such as signal and image …

    研究報告組込みシステム(EMB) 2013-EMB-28(43), 1-6, 2013-03-06

  • Evaluation Environment for Configuration of Floating-Point Unit Arrays  [in Japanese]

    伊藤 勇也 , 高瀬 英希 , 高木 一義 , 高木 直史

    … レイの構成を検討することができる.本稿では,評価環境の適用例を挙げ,アレイの構成やデータ表現の検討における評価環境の有用性を示す.A floating-point unit array that is constructed by connecting floating-point units, is expected to be an excellent architecture for calculating a huge amount of operation in scientific computation such as signal and image …

    研究報告システムLSI設計技術(SLDM) 2013-SLDM-160(43), 1-6, 2013-03-06

  • Design of FPAccA model 2.0 Chip : Reconfigurable Floating-Point-Unit Array  [in Japanese]

    KAWANO Yoichi , OCHI Hiroyuki , TSUDA Takao

    … Field Programmable Accumulator Array(FPAccA), a coarse-grain FPGA architecture, has beenproposed to solve problems with conventional FPGAs such as increasing time taken for placement and routing. … In this paper, FPAccA model 2.0 chip is designed and evaluated, which has a single-presision floating-point unit of IEEE 754 standard in each cell. …

    Technical report of IEICE. VLD 99(530), 45-52, 2000-01-12

    References (4) Cited by (4)

  • Design of FPAccA model 2.0 Chip : Reconfigurable Floating-Point-Unit Array  [in Japanese]

    KAWANO Yoichi , OCHI Hiroyuki , TSUDA Takao

    … Field Programmable Accumulator Array(FPAccA), a coarse-grain FPGA architecture, has been proposed to solve problems with conventional FPGAs such as increasing time taken for placement and routing. … In this paper, FPAccA model 2.0 chip is designed and evaluated, which has a single-presision floating-point unit of IEEE 754 standard in each cell. …

    IEICE technical report. Computer systems 99(532), 45-52, 2000-01-12

    References (4)

  • Design of FPAccA model 2.0 Chip : Reconfigurable Floating-Point-Unit Array  [in Japanese]

    KAWANO Yoichi , OCHI Hiroyuki , TSUDA Takao

    … Field Programmable Accumulator Array(FPAccA), a coarse-grain FPGA architecture, has been proposed to solve problems with conventional FPGAs such as increasing time taken for placement and routing. … In this paper, FPAccA model 2.0 chip is designed and evaluated, which has a single-presision floating-point unit of IEEE 754 standard in each cell. …

    情報処理学会研究報告. SLDM, [システムLSI設計技術] 94, 125-132, 2000-01-11

    References (4)

  • A Reciprocal Number Calculation Circuit Design for FPGA  [in Japanese]

    OGATA W. , KASAHARA H.

    … To cope with these problems, we have been developed an architecture emulator, which is high-performance with floating point arithmetic unit ; … It is combination of S-RAM based large scale FPGAs (Field Programmable Gate Array). … During the execution of real-benchmark program, many amount of floating division operation may be executed. …

    Technical report of IEICE. VLD 98(446), 53-59, 1998-12-10

    References (9)

  • A Reciprocal Number Calculation Circuit Design for FPGA  [in Japanese]

    OGATA W. , KASAHARA H.

    … To cope with these problems, we have been developed and architecture emulator, which is high-performance with floating point arithmetic unit ; … It is combination of S-RAM based large scale FPGAs (Field Programmable Gate Array). … During the execution of real-benchmark program, many amount of floating division operation may be executed. …

    IEICE technical report. Computer systems 98(448), 53-59, 1998-12-10

    References (9)

  • A Reciprocal Number Calculation Circuit Design for FPGA  [in Japanese]

    Ogata W. , Kasahara H.

    … To cope with these problems, we have been developed an architecture emulator, which is high-performance with floating point arithmetic unit, not so expensive cost, reconfigurable easily. … It is combination of S-RAM based large scale FPGAs(Field Programmable Gate Array). … During the execution of real-benchmark program, many amount of floating division operation may be executed. …

    IPSJ SIG Notes 98(113), 53-59, 1998-12-10

  • Implementation of FPGA Based Architecture Test Bed For Multi Processor System  [in Japanese]

    OGATA W. , YAMAMOTO T. , MIZUO M. , KIMURA K. , KASAHARA H.

    … To cope with these problems, we have been planning an architecture emulator, which is high-performance with floating point arithmetic unit; … It is combination of S-RAM based large scale FPGAs (Field Programmable Gate Array). … On the emulator using FPGAs, 32-bit CPU-CORE including Floating-point Unit with 30MIPS/MFLOPS is implemented. …

    IPSJ SIG Notes 128, 79-84, 1998-03-05

    References (4) Cited by (2)

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