Low Power Dissipation of High-Performance VLSI Processor for State-Space Digital Filters

• TSUNEKAWA Yoshitaka

  Faculty of Engineering, Iwate University

• IWAWAKI Michiru

  Faculty of Engineering, Iwate University

• CHIBA Kohji

  Faculty of Engineering, Iwate University

• MIURA Mamoru

  Faculty of Engineering, Iwate University

Bibliographic Information

Other Title

• 制御向き状態空間ディジタルフィルタ用高性能VLSIプロセッサの低消費電力化
• セイギョ ムキ ジョウタイ クウカン ディジタルフィルタヨウ コウセイノウ V

Abstract

State-space digital filters can synthesize the optimal filter structure with respect to overall quantization effects, but have many more multiplications than a canonical structure has. Therefore the sampling rate and the latency become important problems on implementing these filters. Especially for the very long latency the control system becomes unstable when these filters are used in the feedback control systems, such as the robot control system.<br>Previously we proposed a VLSI-oriented highly parallel architecture for state-space digital filters with high sampling rate and small latency. For the purpose of further speeding up and reducing hardware complexity, the distributed arithmetic, of which processing time depends on only word length, was applied to this architecture, making good use of high accuracy of state-space digital filters. Therefore, the very high sampling rate can be implemented independently of the filter order and the numbers of the inputs and outputs.<br>This paper presents a low power dissipation architecture for our proposed VLSI processor of state-space digital filters using distributed arithmetic. To reduce power dissipation, we replace ROMs using in usual distributed arithmetic with optimal circuits of logical gates. In addition, by applying the properties of filter structures to optimal functional circuits, a more decrease in power dissipation becomes possible. As a result, high-performance VLSI processor is implemented, which has very high sampling rate of 3.9MHz (0.6μm CMOS technology) and low power dissipation of about 2.1W in the case where the filter order is 16. This can decrease power dissipation to about 77% when compared to the VLSI processor using ROMs.

Journal

• Transactions of the Society of Instrument and Control Engineers

  Transactions of the Society of Instrument and Control Engineers 34 (11), 1715-1723, 1998

  The Society of Instrument and Control Engineers

Keywords

• state-space digital filters
• distributed arithmetic
• low power dissipation
• filter structure

Details

• CRID: 1390001204501421952
• NII Article ID: 130003791327
• NII Article ID: 10002480281
• NII Book ID: AN00072392
• DOI: 10.9746/sicetr1965.34.1715
• ISSN: 18838189
• ISSN: 04534654
• NDL BIB ID: 4606721
• Web Site: https://ndlsearch.ndl.go.jp/books/R000000004-I4606721
• Web Site: https://www.jstage.jst.go.jp/article/sicetr1965/34/11/34_11_1715/_pdf
• Data Source:
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  • CiNii Articles
• Abstract License Flag: Disallowed