High-speed Bus Circuit Methodology

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  • 高速バス回路方式
  • コウソク バス カイロ ホウシキ

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Abstract

High-speed bus circuit is the key especially for high performance systems built-in processors. But the conventional bus circuits with low power dissipation have the problem of the ringing and dips caused by reflection, then the bus transfer rate cannot reach 100MHz. The Lattice Diagram has been used, but it shows only rough behavior of reflection, or cannot show graphically the relation between the timing and waveforms for reflection.<br>This paper proposes not only the bus circuit with non-power-dissipated termination that can achieve the transfer rate of over 100MHz which is 2.5_??_3 times faster than the conventional low power bus circuit, but also the newly-devised Lattice Diagram that can clarify graphically the relation between the reflection timing and the waveforms distorted by reflection. SPICE simulation was made to examine the transfer rate for each bus circuit. The bus circuit with non-power-dissipated termination was confirmed 167MHz transfer rate experimentally.

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