書誌事項
- タイトル別名
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- Design and VLSI Evaluation of High-Speed Cellular Array Divider with Selection Function
- センタクガタ セル ハイレツ コウソク ジョザンキ ノ セッケイ ト VLSI
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In recent years, a very high-speed divider is required in real-time applications of digital signal processing and robot control and so on. In this paper, a high-speed cellular array divider with selection function is proposed, which is based on the non-restoring algorithm and can deal with both fixed-point and negative operands in two's complement form. This divider uses new techniques which can generate in parallel both a quotient bit of one row and a partial remainder and CLA bit of its next row. Moreover the delay time of the proposed divider is calculated in terms of a delay of one unit such as NAND gate. Finally, by using PARTHENON, a CAD (Computer Aided Design) system for VLSI, this divider is designed and evaluated. As a result, elimination of delay time for even rows becomes possible. Thus, the delay time can decrease by approximately one-half of the high-speed divider proposed by Cappa and Hamacher which uses the most general high-speed techniques of carry-save and CLA.
収録刊行物
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- 電気学会論文誌Ｃ（電子・情報・システム部門誌）
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電気学会論文誌Ｃ（電子・情報・システム部門誌） 117 (6), 760-767, 1997
一般社団法人 電気学会
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詳細情報 詳細情報について
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- CRID
- 1390001204608056320
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- NII論文ID
- 130006843809
- 10004437990
- 10002810545
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- NII書誌ID
- AN10065950
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- ISSN
- 13488155
- 03854221
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- NDL書誌ID
- 4216204
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- データソース種別
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- JaLC
- NDL
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