Proposal of Improvement of Arc Velocity travelling between Parallel Conductors in Piling-up Arrangement
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- Inaba Tsuginori
- Chuo University
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- Oi Hiroyuki
- Chuo University
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- Ito Amane
- Chuo University
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- Hasegawa Kenichi
- Saneisha-Seisakusho
Bibliographic Information
- Other Title
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- 積層配置による平行導体間アークの駆動速度向上対策の提案
- セキソウ ハイチニヨルヘイコウ ドウタイ カン アーク ノ クドウ ソクド コ
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Abstract
The travelling of an arc between parallel electrodes can be used in order W suppress the fault current by inserting the electrode, resistance to the fault circuit, where the arc velocity plays the most important role. In order to increase the arc velocity a special piling-up type has been theoretically recommended, the arc velocity of which is expected to become about 22% faster than that in the ordinary parallel type.
Journal
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- IEEJ Transactions on Power and Energy
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IEEJ Transactions on Power and Energy 118 (10), 1078-1084, 1998
The Institute of Electrical Engineers of Japan
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Details
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- CRID
- 1390282679581555584
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- NII Article ID
- 130006841286
- 10005721303
- 10002876916
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- NII Book ID
- AN10136334
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- ISSN
- 13488147
- 03854213
- http://id.crossref.org/issn/03854213
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- NDL BIB ID
- 4565891
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- Data Source
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- JaLC
- NDL
- Crossref
- CiNii Articles
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- Abstract License Flag
- Disallowed