ウェハ保管環境の MOS デバイス特性への影響  [in Japanese] Influence of Wafer Storage Environment on MOS Device Characteristics  [in Japanese]

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Abstract

The influence of wafer storage environment on oxidation and organic contamination of Si surfaces has been investigated. And the electronic reliability of thin (2.8 nm) SiO<SUB>2</SUB> films of metal-oxide-semiconductor (MOS) capacitors and MOS transistors has been measured as a function of the storage method. We found that shielding wafers from visible light is effective to prevent oxidation of silicon. Hydrogen terminated <I>p</I>-Si (100) (8 ∼ 12 Ωcm) wafers were stored in wafer boxes under various brightness levels. The oxidation rate in a dark box (∼ 0 lx) is found to be about one order of magnitude as small as that in a light box (∼ 1,000 lx). The MOS capacitors were fabricated by adding a storage process with various contamination levels before gate oxidation. It was indicated that for samples stored in the polyethersulfone (PES) box with a UV/photoelectron cleaning unit, the organic contamination level was substantially reduced, resulting in an improvement of the time dependent dielectric breakdown characteristics of the gate oxides. Furthermore we fabricated <I>n</I>-channel MOS transistors and investigated the influence of the organic contaminant before and after the gate oxidation on hot-electron degradation of the oxide. The wafer surfaces were contaminated with organic gases during the storage in a front opening unified pod (FOUP) made of polycarbonate for 6 h. In the result, the neutral traps were generated by hot-electron injection. It was shown that the density of the generated traps was larger for the pre-oxidation contamination than for the post-oxidation contamination. The model for the trap generation by the organic contamination was also discussed.

Journal

  • Earozoru Kenkyu

    Earozoru Kenkyu 17(2), 96-104, 2002-06-20

    Japan Association of Aerosol Science and Technology

References:  28

  • <no title>

    Semiconductor Industry Association

    International Technology Roadmap for Semiconductors 1999 Edition, 1999

    Cited by (2)

  • <no title>

    Semiconductor Industry Association

    International Technology Roadmap for Semiconductors 2001 Edition, 2001

    Cited by (2)

  • <no title>

    MIHIR P.

    NIKKEI MICRODEVICES 11, 11, 1999

    Cited by (1)

  • <no title>

    300mm Hondoutai Gijutsu Renrakukai

    2nd Lecture, ICs Factory Design for 300 mm Wafer Line Standardizing Study, 1996

    Cited by (1)

  • <no title>

    TOBIMATSU H.

    Proc. Int. Symp. on Semiconductor Manufacturing, 1997

    Cited by (1)

  • <no title>

    YOKOYAMA S.

    Proc. Int. Symp. on Semiconductor Manufacturing, 169-172, 1999

    Cited by (1)

  • <no title>

    YOSHINO T.

    Earozoru Kenkyu 16, 57-64, 2001

    Cited by (1)

  • <no title>

    FUJII T.

    Earozoru Kenkyu 13, 110-118, 1998

    Cited by (1)

  • <no title>

    WAKABAYASHI T.

    Meet. Abstr. Inst. Electrical Eng. Jpn., 55-60, 1996

    Cited by (2)

  • <no title>

    SUNADA T.

    Jpn.J.Appl.Phys. 29, L2408, 1990

    Cited by (4)

  • <no title>

    OKADA C.

    Jpn. J. Appl. Phys. 32, L1031, 1993

    Cited by (4)

  • <no title>

    TORIUMI A.

    J. Vac. Sci. Technol. B14, 4026-4030, 1996

    Cited by (1)

  • <no title>

    FUIJII T.

    Proc. of 18th Conf. of Air Cleaning Asoc. Jpn., 233-239, 2000

    Cited by (1)

  • <no title>

    MORITA M.

    J. Appl. Phys. 68, 1272-1274, 1990

    Cited by (1)

  • <no title>

    HIROSE M.

    Handoutai Kenkyu 36, 263-284, 1992

    Cited by (1)

  • <no title>

    TAKEDA E.

    Hot-Carrier Effects in MOS Devices, 1995

    Cited by (4)

  • <no title>

    EITAN B.

    Tech. Digest of Int. Electron Devices Meeting (IEDM), 604-607, 1981

    Cited by (1)

  • <no title>

    AKERS L. A.

    Solid-State Electronics 25, 621, 1982

    Cited by (1)

  • <no title>

    YOUNG D. R.

    Inst. Phys. Conf. Ser. 50, 28, 1980

    Cited by (2)

  • <no title>

    DIMARIA D. J.

    The Physics of SiO_2 and its Interfaces 160, 1978

    Cited by (3)

  • <no title>

    MOZZI R. L.

    J. Appl. Crystallogr. 2, 164, 1969

    Cited by (8)

  • <no title>

    YOKOYAMA S.

    Proc. IEST, 1998, 1998

    Cited by (2)

  • <no title>

    YOSHINO T.

    Jpn. J. Appl. Phys. 40, 2849-2853, 2001

    DOI  Cited by (1)

  • <no title>

    YOSHINO T.

    Jpn. J. Appl. Phys. 40, 2223-2224, 2001

    DOI  Cited by (1)

  • <no title>

    YASAKA T.

    IEICE Trans. Electron. C75, 764-769, 1992

    Cited by (1)

  • <no title>

    HIROSE M.

    Mater. Sci. Eng. B41, 35-38, 1996

    Cited by (5)

  • <no title>

    NICOLLIAN E. H.

    J.Appl.Phys. 42, 5654, 1971

    DOI  Cited by (8)

  • Threshold-voltage instability in MOSFET's due to channel hot-hole emission

    FAIR R. B.

    IEEE Trans. Electron Devices 28, 83-94, 1981

    Cited by (6)

Codes

  • NII Article ID (NAID)
    10008837105
  • NII NACSIS-CAT ID (NCID)
    AN10041511
  • Text Lang
    JPN
  • Article Type
    ART
  • ISSN
    09122834
  • NDL Article ID
    6193534
  • NDL Call No.
    Z17-1062
  • Data Source
    CJP  NDL  J-STAGE 
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