Heuristic algorithms for FBDD node minimization with application to pass-transistor-logic and DCVS synthesis

Author(s)

Journal

  • Proc. SASIMI Workshop

    Proc. SASIMI Workshop, 96-101, 1996

Cited by:  1

  • Bi-Partition of Shared Binary Decision Diagrams

    MATSUURA Munehiro , SASAO Tsutomu , BUTLER Jon T. , IGUCHI Yukihiro

    IEICE transactions on fundamentals of electronics, communications and computer sciences 85(12), 2693-2700, 2002-12-01

    References (23)

Codes

  • NII Article ID (NAID)
    10010453255
  • Article Type
    Proceedings
  • Data Source
    CJPref 
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