Lower Boundary of Supply Voltage in Digital ULSI Based on the Communication Theory

• Nakase Hiroyuki

  Research Institute of Electrical Communication, Tohoku University

• Sagitani Tsuyoshi

  Research Institute of Electrical Communication, Tohoku University

• Masu Kazuya

  Research Institute of Electrical Communication, Tohoku University

• Tsubouchi Kazuo

  Research Institute of Electrical Communication, Tohoku University

抄録

We have proposed a theoretical design method for the lower boundary of supply voltage using the universal E_b⁄N₀-bit error rate (BER) characteristics from the system viewpoint. In order to achieve the system error rate of less than 10⁻¹⁰ with the conditions of 10 years term, 10 GHz clock and 10⁶ gate, the bit error rate of a gate should be less than 10⁻³⁴. For a BER of 10⁻³⁴, V_DD should be larger than 0.1 V for 0.13 μm complementally metal-oxide-silicon (CMOS) LSI. For 0.05 μm CMOS of next generation, V_DD should be larger than 0.2 V under the ideal thermal noise environment. The measured E_b⁄N₀-BER characteristics of CMOS circuits as a function of supply voltage have agree well with the theoretical value.

収録刊行物

• Japanese Journal of Applied Physics

  Japanese Journal of Applied Physics 42 (10A), L1133-L1135, 2003

  The Japan Society of Applied Physics

キーワード

• CMOS LSI
• lower boundary of supply voltage
• <I>E</I><SUB>b</SUB>⁄<I>N</I><SUB>0</SUB> characteristics

詳細情報

• CRID: 1390282681241267456
• NII論文ID: 10011766697
• NII論文ID: 210000054670
• NII論文ID: 130004530083
• NII書誌ID: AA11906093
• DOI: 10.1143/jjap.42.l1133
• ISSN: 13474065
• ISSN: 00214922
• NDL書誌ID: 6705643
• Web Site: http://id.ndl.go.jp/bib/6705643
• Web Site: https://ndlsearch.ndl.go.jp/books/R000000004-I6705643
• Web Site: http://stacks.iop.org/1347-4065/42/i=10A/a=L1133/pdf
• 本文言語コード: en
• データソース種別:
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  • NDL
  • Crossref
  • CiNii Articles
• 抄録ライセンスフラグ: 使用不可