Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model

• KITAI Tomoya

  Graduate School of Information Science and Engineering, Dept. of Computer Science, Tokyo Institute of Technology

• OGURO Yusuke

  Graduate School of Information Science and Engineering, Dept. of Computer Science, Tokyo Institute of Technology

• YONEDA Tomohiro

  Infrastructure Systems Research Division, National Institute of Informatics

• MERCER Eric

  Brigham Young University

• MYERS Chris

  Department of Electrical and Computer Engineering, University of Utah

Journal

• IEICE transactions on information and systems

  IEICE transactions on information and systems 86 (12), 2601-2611, 2003-12-01

Keywords

• Level-oriented model
• timed asynchronous circuits
• formal verification
• time Petri nets

Details

• CRID: 1570291225166084352
• NII Article ID: 10012560062
• NII Book ID: AA10826272
• ISSN: 09168532
• Text Lang: en
• Data Source:
  • CiNii Articles