Impact of Ti Deposition and Subsequent RTA Process on Contact Resistivity Characteristics of W-Bit Line in Sub-Micron Dynamic Random Access Memory

この論文にアクセスする

この論文をさがす

著者

    • Kim Nam-Sung Kim Nam-Sung
    • Process Integration Department, Systems on Silicon Manufacturing Co. Pte. Ltd., 70 Pasir Ris Drive 1, 519527, Singapore
    • Kim Il-Gweon Kim Il-Gweon
    • Memory R&D Division, Hynix Semiconductor Inc., 1 Hyangjeong-dong, Heungduk-gu, Cheongju, Chungbuk 361-725, Korea
    • Park Joo-Seog
    • Memory R&D Division, Hynix Semiconductor Inc., 1 Hyangjeong-dong, Heungduk-gu, Cheongju, Chungbuk 361-725, Korea

抄録

We have intensively investigated the impact of Titanium (Ti) deposition condition along with optimal Ti thickness and subsequent rapid thermal annealing (RTA) process on each contact resistivity (Rc) characteristics of W-bit line in sub-micron dynamic random access memory (DRAM) technology. We found out that low pressure (LP) Ti deposition method with a subsequent RTA temperature above critical value is very efficient to improve the uniformity of Ti deposited thickness inside the contact hole as well as to remove the agglomeration in the contact area of periphery n+ and p+ active regions, resulting in the dramatic Rc reduction with a good uniformity across a wafer. In addition, the optimized condition of Ti deposition and RTA process suitable to 0.15 μm DRAM and beyond is proposed to reduce W-bit line Rc of cell and periphery areas simultaneously, while still keeping the good electrical properties for other significant parameters such as junction leakage and data retention time.

収録刊行物

  • Japanese journal of applied physics. Pt. 1, Regular papers & short notes

    Japanese journal of applied physics. Pt. 1, Regular papers & short notes 42(11), 6784-6789, 2003-11-15

    公益社団法人 応用物理学会

参考文献:  9件中 1-9件 を表示

  • <no title>

    KANG H. K.

    Electron Devices Meeting, 1994. Tech. Dig. Int. 635, 1994

    被引用文献1件

  • <no title>

    JIN B. J.

    IEEE Int. VLSI Technology, 2001. Dig. Tech. Pap. 127, 2001

    被引用文献1件

  • <no title>

    PARK Y. K.

    Electron Devices Meeting, IEDM'02. Tech. Dig. Int. 819, 2002

    被引用文献1件

  • <no title>

    KIM D. C.

    Electron Devices Meeting, IEDM'01 Tech. Dig. Int. 18.3.1, 2001

    被引用文献1件

  • <no title>

    ASANO I.

    Int. Conf. SSDM, 2001 30, 2001

    被引用文献1件

  • <no title>

    HAN J. S.

    Ion Implantation Technology, Conf., 2000 83, 2000

    被引用文献1件

  • <no title>

    HA D.

    IEEE Trans. Electron Devices 47, 1499, 2000

    被引用文献1件

  • <no title>

    IM H.

    Proc. 2002 Int. Symp. Low Power Electronics and Design 13, 2002

    被引用文献1件

  • <no title>

    LEONG M.

    Tech. Dig. IEDM., 1998 733, 1998

    被引用文献1件

各種コード

  • NII論文ID(NAID)
    10012563700
  • NII書誌ID(NCID)
    AA10457675
  • 本文言語コード
    EN
  • 資料種別
    ART
  • 雑誌種別
    大学紀要
  • ISSN
    0021-4922
  • NDL 記事登録ID
    6752067
  • NDL 雑誌分類
    ZM35(科学技術--物理学)
  • NDL 請求記号
    Z53-A375
  • データ提供元
    CJP書誌  NDL  J-STAGE  JSAP 
ページトップへ