A Realization of Theoretical Maximum Performance in IPSec on Gigabit Ethernet

• Onuki Atsushi

  Information Technology R&D Center, Mitsubishi Electric Corporation

• Takeuchi Kiyofumi

  Information Technology R&D Center, Mitsubishi Electric Corporation

• Inada Toru

  Information Technology R&D Center, Mitsubishi Electric Corporation

• Tokiniwa Yasuhisa

  Information Technology R&D Center, Mitsubishi Electric Corporation

• Ushirozawa Shinobu

  Information Technology R&D Center, Mitsubishi Electric Corporation

Bibliographic Information

Other Title

• ギガビットイーサネットにおけるＩＰＳｅｃ論理限界性能の実現
• ギガビットイーサネット ニ オケル IPSec ロンリ ゲンカイ セイノウ ノ ジツゲン

Abstract

This paper describes “IPSec(IP Security) VPN system" and how it attains a theoretical maximum performance on Gigabit Ethernet. The Conventional System is implemented by software. However, the system has several bottlenecks which must be overcome to realize a theoretical maximum performance on Gigabit Ethernet. Thus, we newly propose IPSec VPN System with the FPGA(Field Programmable Gate Array) based hardware architecture, which transmits a packet by the pipe-lined flow processing and has 6 parallel structure of encryption and authentication engines. We show that our system attains the theoretical maximum performance in the short packet which is difficult to realize until now.

Journal

• IEEJ Transactions on Electronics, Information and Systems

  IEEJ Transactions on Electronics, Information and Systems 124 (8), 1533-1537, 2004

  The Institute of Electrical Engineers of Japan

Keywords

• IPSec
• Gigabit Ethernet
• VPN
• FPGA

Details

• CRID: 1390001204603998464
• NII Article ID: 10013325101
• NII Book ID: AN10065950
• DOI: 10.1541/ieejeiss.124.1533
• ISSN: 13488155
• ISSN: 03854221
• NDL BIB ID: 7052038
• Web Site: https://ndlsearch.ndl.go.jp/books/R000000004-I7052038
• Web Site: http://www.jstage.jst.go.jp/article/ieejeiss/124/8/124_8_1533/_pdf
• Text Lang: ja
• Data Source:
  • JaLC
  • NDL
  • Crossref
  • CiNii Articles
• Abstract License Flag: Disallowed