3次元実装に用いる高アスペクト比貫通電極の銅穴埋めめっき Copper Via Filling Electrodeposition of High Aspect Ratio Through Chip Electrodes Used for the Three Dimensional Packaging

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Through chip electrodes with high aspect ratios used for three dimensional packaging can offer the shortest interconnection and reduce signal delay. Copper has good-compatibility to conventional multi layer interconnection in LSI and BEOL (back end of line process). In this work, filling vias with higher aspect ratio, 10μm in square and 70 μm in depth, used for through chip electrodes was investigated. Removing overhang at via top is important to achieve perfect via fill of 10μm in square and 70 μm in depth. With testing a series of electrodeposition conditions, conformal electrodeposits were obtained. With those conformal electrodeposits, seams and voids always remain at the via center. Perfect via filling without seams or voids was achieved by increasing leveler of JGB concentration to 30 mg/L. The electrodeposition time was reduced to 3.5hrs by using two steps pulse reverse current.

収録刊行物

  • エレクトロニクス実装学会誌

    エレクトロニクス実装学会誌 6(7), 596-601, 2003-11-01

    社団法人エレクトロニクス実装学会

参考文献:  11件中 1-11件 を表示

被引用文献:  6件中 1-6件 を表示

各種コード

  • NII論文ID(NAID)
    10013959153
  • NII書誌ID(NCID)
    AA11231565
  • 本文言語コード
    JPN
  • 資料種別
    ART
  • ISSN
    13439677
  • NDL 記事登録ID
    6752505
  • NDL 雑誌分類
    ZN33(科学技術--電気工学・電気機械工業--電子工学・電気通信)
  • NDL 請求記号
    Z74-B258
  • データ提供元
    CJP書誌  CJP引用  NDL  NII-ELS 
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