A single-electron-transistor logic gate family and its application-Part II : Design and simulation of a 7-3 parallel counter with a linear summation and MV latch functions

• INOKAWA H.

Journal

• Proc. 34th IEEE Int. Symp. on Multiple-Valued Logic, May 2004

  Proc. 34th IEEE Int. Symp. on Multiple-Valued Logic, May 2004 2004

Details

• CRID: 1572543024777679488
• NII Article ID: 10014689174
• Data Source:
  • CiNii Articles