Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh(Memory, <Special Section>Low-Power LSI and Low-Power IP)

• NODA Hideyuki

  Renesas Technology Corp.

• INOUE Kazunari

  Renesas Technology Corp.

• MATTAUSCH Hans Jurgen

  Hiroshima University

• KOIDE Tetsushi

  Hiroshima University

• DOSAKA Katsumi

  Renesas Technology Corp.

• ARIMOTO Kazutami

  Renesas Technology Corp.

• FUJISHIMA Kazuyasu

  Renesas Technology Corp.

• ANAMI Kenji

  Renesas Technology Corp.

• YOSHIHARA Tsutomu

  Waseda University

抄録

This paper describes a dynamic TCAM architecture with planar complementary capacitors, transparently scheduled refresh (TSR), autonomous power management (APM) and address-input-free writing scheme. The complementary cell structure of the planar dynamic TCAM (PD-TCAM) allows small cell size of 4.79μm^2 in 130nm CMOS technology, and realizes stable TCAM operation even with very small storage capacitance. Due to the TSR architecture, the PD-TCAM maintains functional compatibility with a conventional SRAM-based TCAM. The combined effects of the compact PD-TCAM array matrix and the APM technique result in up to 50% reduction of the total power consumption during search operation. In addition, an intelligent address-input-free writing scheme is also introduced to facilitate the PD-TCAM application for the user. Consequently the proposed architecture is quite attractive for realizing compact and low-power embedded TCAM macros for the design of system VLSI solutions in the field of networking applications.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 88 (4), 622-629, 2005-04-01

  一般社団法人電子情報通信学会

キーワード

• CMOS
• Ternary CAM
• network
• refresh

詳細情報

• CRID: 1573105975069575040
• NII論文ID: 10016563199
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: en
• データソース種別:
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