High Ruggedness Power MOSFET Design by a Self-Align p^+ Process(Power Devices, <Special Section>Fundamental and Application of Advanced Semiconductor Devices)

• CHIEN Feng Tso

  Dept. of Electronic Engineering, Feng Chia University

• LAI Ming Hung

  R&D Dept., Chino-Excel Technology Corp.

• SU Shih Tzung

  R&D Dept., Chino-Excel Technology Corp.

• TU Kou Way

  R&D Dept., Chino-Excel Technology Corp.

• CHENG Ching Ling

  R&D Dept., Chino-Excel Technology Corp.

抄録

A new high ruggedness Power MOSFET structure with a planar oxide self align p^+ implant structure is proposed and discussed. We compare the proposed self-align process with the conventional p^+ MASK process and contact p^+ implant process. It is shown that the self align implant structure with a wide p^+ area can reduce the parasitic BJT effect and, therefore, improve the device's avalanche energy capability, which is required for inductive load circuits. Based on the unclamped inductive load switching measurement results, the proposed device avalanche energy with self align p^+ implant process is improved about 355% as compared to the traditional one.

収録刊行物

• IEICE transactions on electronics

  IEICE transactions on electronics 88 (4), 694-698, 2005-04-01

  一般社団法人電子情報通信学会

キーワード

• Power MOSFET
• unclamped inductive load switching (UIS)
• ruggedness

詳細情報

• CRID: 1571698600186174848
• NII論文ID: 10016563349
• NII書誌ID: AA10826283
• ISSN: 09168524
• 本文言語コード: en
• データソース種別:
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