A Novel Process for Fabrication of Gated Silicon Field Emitter Array Taking Advantage of Ion Bombardment Retarded Etching

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  • Tanii Takashi
    School of Science and Engineering, Waseda University Nanotechnology Research Center, Waseda University
  • Fujita Satoru
    School of Science and Engineering, Waseda University
  • Numao Yoshiteru
    School of Science and Engineering, Waseda University
  • Matsuya Iwao
    Kagami Memorial Laboratory for Materials Science and Technology, Waseda University
  • Sakairi Mitsuaki
    School of Science and Engineering, Waseda University
  • Masahara Meishoku
    Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology
  • Ohdomari Iwao
    School of Science and Engineering, Waseda University Kagami Memorial Laboratory for Materials Science and Technology, Waseda University Nanotechnology Research Center, Waseda University

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A novel process for the fabrication of a gated silicon field emitter array is proposed. The process involves complete self-alignment of gate electrodes taking advantage of ion bombardment retarded etching. The ion-irradiated regions serve as masks for subsequent silicon etching resulting in the formation of tabletop structures. The structures are suitable for both the formation of pyramidal emitters and the arrangement of gate electrodes adjacent to each emitter. We integrate this silicon etching into a self-align process for the fabrication of gated emitter array. The emission characteristics of 100 emitters are tested, and the emission at a gate voltage of 30 V is detected. The results indicate that the proposed process is applicable to the fabrication of gated silicon emitters.

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