Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders(Digital Circuits and Computer Arithmetic, <Special Section>Recent Advances in Circuits and Systems-Part 1)

• DEBNATH Debatosh

  Department of Computer Science and Engineering, Oakland University

• SASAO Tsutomu

  Department of Computer Science and Electronics, Kyushu Institute of Technology

抄録

This paper presents a design method for three-level programmable logic arrays (PLAs), which have input decoders and two-input EXOR gates at the outputs. The PLA realizes an EXOR of two sum-of-products expressions (EX-SOP) for multiple-valued input two-valued output functions. We developed an output phase optimization method for EX-SOPs where some outputs of the function are minimized in the complemented form and presented techniques to minimize EX-SOPs for adders by using an extension of Dubrova-Miller-Muzio's AOXMIN algorithm. The proposed algorithm produces solutions with a half products of AOXMIN-like algorithm in 250 times shorter time for large adders with two-valued inputs. We also proved that an n-bit adder with two-valued inputs requires at most 3・2^<n-2>+7n-5 products in an EX-SOP while it is known that a sum-of-products expression (SOP) requires 6・2^n-4n-5 products.

収録刊行物

• IEICE transactions on information and systems

  IEICE transactions on information and systems 88 (7), 1492-1500, 2005-07-01

  一般社団法人電子情報通信学会

キーワード

• three-level network
• logic minimization
• adder
• programmable logic

詳細情報

• CRID: 1573950400019573248
• NII論文ID: 10016777277
• NII書誌ID: AA10826272
• ISSN: 09168532
• 本文言語コード: en
• データソース種別:
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