Novel Fabrication Process to Realize Ultra-thin (EOT=0.7nm) and Ultra-low Leakage SiON Gate Dielectrics

• MATSUSHITA D.

収録刊行物

• Symposium on VLSI Technology, Digest of Technical Papers, 2004

  Symposium on VLSI Technology, Digest of Technical Papers, 2004 2004

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• CRID: 1572543025265272704
• NII論文ID: 10018156850
• データソース種別:
  • CiNii Articles